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timgroth
Visitor
Visitor
14,855 Views
Registered: ‎09-30-2009

simple and gate can't be output in vhdl

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Making and gate with VHDL and synthesizer demands that the output be inout or buffer instead of out. Examples in books etc show that out is fine. Then I changed output to inout and get the following warning. WARNING:Xst:2170 - Unit andGate_VHDL : the following signal(s) form a combinatorial loop: C.  When I simulate this, C won't go high when A and B are high. 
 

 

Here is the code

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity andGate_VHDL is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end andGate_VHDL;

architecture test of andGate_VHDL is

begin

C <= (B AND C);

end test;

****

Results in this error

 

HDLCompiler:288 - Cannot read from 'out' object c ; use 'buffer' or 'inout'

I converted this to verilog and had no warnings or errors and it simulated fine.  Unfortunately I need to use VHDL at the moment.  So someone help me get through this simple and gate please. 

 

 

 

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bassman59
Historian
Historian
18,559 Views
Registered: ‎02-25-2008

timgroth wrote:

Making and gate with VHDL and synthesizer demands that the output be inout or buffer instead of out. Examples in books etc show that out is fine. Then I changed output to inout and get the following warning. WARNING:Xst:2170 - Unit andGate_VHDL : the following signal(s) form a combinatorial loop: C.  When I simulate this, C won't go high when A and B are high. 
 

 

Here is the code

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity andGate_VHDL is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end andGate_VHDL;

architecture test of andGate_VHDL is

begin

C <= (B AND C);

end test;

****

Results in this error

 

HDLCompiler:288 - Cannot read from 'out' object c ; use 'buffer' or 'inout'

I converted this to verilog and had no warnings or errors and it simulated fine.  Unfortunately I need to use VHDL at the moment.  So someone help me get through this simple and gate please. 

 

 

 


This is really basic VHDL 101. Please, buy a copy of a good VHDL text and read it.

 

VHDL does not allow you to "read" a signal that is declared as an output port. (Think hardware: why can't you do this in real hardware?) So the simple and correct solution is to declare an internal (to the entity's architecture) signal and use that signal as the target (left-hand-side) of the assignment. Then you write another assignment that connects the internal signal to the output port.

 

The combinational loop warning is instructive, too: why do you think you get this warning? Again: think hardware. You really must understand why this is a problem.

 

-a

 

ps: so what's the signal A supposed to do in your entity? It's not used.

----------------------------Yes, I do this for a living.

View solution in original post

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3 Replies
bassman59
Historian
Historian
18,560 Views
Registered: ‎02-25-2008

timgroth wrote:

Making and gate with VHDL and synthesizer demands that the output be inout or buffer instead of out. Examples in books etc show that out is fine. Then I changed output to inout and get the following warning. WARNING:Xst:2170 - Unit andGate_VHDL : the following signal(s) form a combinatorial loop: C.  When I simulate this, C won't go high when A and B are high. 
 

 

Here is the code

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity andGate_VHDL is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end andGate_VHDL;

architecture test of andGate_VHDL is

begin

C <= (B AND C);

end test;

****

Results in this error

 

HDLCompiler:288 - Cannot read from 'out' object c ; use 'buffer' or 'inout'

I converted this to verilog and had no warnings or errors and it simulated fine.  Unfortunately I need to use VHDL at the moment.  So someone help me get through this simple and gate please. 

 

 

 


This is really basic VHDL 101. Please, buy a copy of a good VHDL text and read it.

 

VHDL does not allow you to "read" a signal that is declared as an output port. (Think hardware: why can't you do this in real hardware?) So the simple and correct solution is to declare an internal (to the entity's architecture) signal and use that signal as the target (left-hand-side) of the assignment. Then you write another assignment that connects the internal signal to the output port.

 

The combinational loop warning is instructive, too: why do you think you get this warning? Again: think hardware. You really must understand why this is a problem.

 

-a

 

ps: so what's the signal A supposed to do in your entity? It's not used.

----------------------------Yes, I do this for a living.

View solution in original post

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timgroth
Visitor
Visitor
14,848 Views
Registered: ‎09-30-2009

Ok got it.  I have to apologize for this post.  I made a typo and somehow didn't see it before I posted.

The code was of course suppose to be

 

C <= (A AND B);

 

Now all the warnings errors are gone and it simulates correctly.  Hopefully I will get more comfortable with VHDL syntax soon so that I can see what I'm actually doing.

Thanks for your help.

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gszakacs
Instructor
Instructor
14,841 Views
Registered: ‎08-14-2007

If it were Verilog, you'd still get the combinatorial loop, but it would be perfectly OK to have feedback

from a module output.  I think VHDL is a bit over-restrictive in this sense.  Certainly for any module

not directly connected to the device pins you should be able to use the value of module outputs.  And

the last device I used that didn't have feedback on all of its output pins was a PAL16L8.  Even so I would

expect a reasonable synthesis tool to replicate the output function for internal use.

 

Just my 2 cents.

 

In any case the combinatorial loop warning should help you find dumb mistakes like typos.

 

regards,

Gabor

-- Gabor
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