02-01-2013 09:48 AM
I am running Vivado 2012.4 32-bit on my 64-bit machine (because the 64-bit Vivado quits with an error every time I launch it. I read something about replacing some dll with a dll from a working machine. But this is the only machine I have access to.).
So the design is a mix of system verilog and verilog RTL. I have set those .v files as type "SystemVerilog". After that I was able to run Design Elaboration Successfully.
In the constraints file, I have simply put just the create_clock command.
The synthesis is running; I see the "Running synth_design" with the green progress bar on the top right but I am not seeing any progress on the log tab or any hard disk write activity.
This has been the case since about an hour. How do I know where that got stuck and how can I resolve it? Thanks!
10-25-2013 06:36 PM
10-28-2013 11:49 PM