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Visitor
Visitor
6,581 Views
Registered: ‎01-31-2013

synth_design apparently getting stuck [Vivado 2012.4]

Hi,

 

I am running Vivado 2012.4 32-bit on my 64-bit machine (because the 64-bit Vivado quits with an error every time I launch it. I read something about replacing some dll with a dll from a working machine. But this is the only machine I have access to.).

 

So the design is a mix of system verilog and verilog RTL. I have set those .v files as type "SystemVerilog". After that I was able to run Design Elaboration Successfully. 

 

In the constraints file, I have simply put just the create_clock command.

 

The synthesis is running; I see the "Running synth_design" with the green progress bar on the top right but I am not seeing any progress on the log tab or any hard disk write activity. 

 

This has been the case since about an hour. How do I know where that got stuck and how can I resolve it? Thanks!

 

 

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4 Replies
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Visitor
Visitor
6,576 Views
Registered: ‎01-31-2013

Re: synth_design apparently getting stuck [Vivado 2012.4]

From the runme.log, I can see that it has got stuck at "Start Technology Mapping" stage in synthesis.
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Explorer
Explorer
6,554 Views
Registered: ‎09-06-2012

Re: synth_design apparently getting stuck [Vivado 2012.4]

Hi,

 

Could please try to run any example design with vivado.check whether you are facing the same issue or not.

 

Ankury

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Visitor
Visitor
6,047 Views
Registered: ‎10-01-2013

Re: synth_design apparently getting stuck [Vivado 2013.2]

Hi,

 

Seems like a similar issue - Vivado just "runs" synth_design - no errors, no warnings beyond this.  Attached is the runme.log - sits here forever with no indication as to why.

 

Please help.

 

David.

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Xilinx Employee
Xilinx Employee
6,029 Views
Registered: ‎07-01-2010

Re: synth_design apparently getting stuck [Vivado 2013.2]

Hi David,

Can you please share the project Archive so that i can check the details and get back to you?
What is the -flatten_hierarchy value in your project settings ?
Can you try using the value full/none and see if this helps?

Regards,
Achutha
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