UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Voyager
Voyager
6,729 Views
Registered: ‎10-06-2015

vhdl array question

I need to generate select lines for 128 multiplexors.  I thought of creating an array [muxsel(127 downto 0)].  Based on an input value of 0 to 127 I would then set muxsel bits appropriately; example if I receieved and input value of 15 I would set

 muxsel( 127 downto 15 )=>1,  others =>0.

 

I can't seem to figure out how to place a signal / variable into the array, example

muxsel <= (127 downto X => '0', others => '1');

 

After some research my issues may be related to complex constructs that Vivado doesn't yet support:

http://www.xilinx.com/support/answers/52302.html

 

Does anyone have suggestions of a work around if the problem is the Vivado sysnthesis engine?  IIt appears this has been an issue for a bit:

https://forums.xilinx.com/t5/Synthesis/Vivado-2014-2-Synth-8-561-range-expression-could-not-be-resolved/td-p/562555

0 Kudos
2 Replies
Highlighted
Participant pete_128
Participant
6,708 Views
Registered: ‎04-02-2016

Re: vhdl array question

 

signal input : std_logic_vector(6 downto 0); --your input signal
signal output : std_logic_vector(127 downto 0); --your one-hot outputs

process(input) is begin
    outputs <= (others => '0');
    for I in 0 to 127 loop
        if I = conv_integer(input) then
            outputs(I) = '1';
        end if;
    end loop;
end process;

Something like this might work. You coudl try ditching the loop, and just use conv_integer on the input to index into the array directly, but synthesis has barfed on me for that in the past (and gives similar errors to the one you linked in the AR).

0 Kudos
Voyager
Voyager
6,701 Views
Registered: ‎10-06-2015

Re: vhdl array question

in one of the post it was suggested to write a case statement to work around this Vivado deficiency.  In the middle of that now.  On a small scale it worked now I have to expand on it quite a bit.

0 Kudos