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Visitor marinamarti
Visitor
92 Views
Registered: ‎05-12-2019

vivado is removing usefull "logic" (all the design)

Hello! I have designed a simple 5-stage MIPS processor with VHDL, and the testbench works fine, but synthesis removes all the logic, because it is "unused"! I don't know why, I have changed the code lots of times but I cannot find the problem! Please could you help me to find the problem that causes the design to be removed?

 

Thanks a lot!

Here is the link to the project:

https://drive.google.com/open?id=1Rde41LUgT_AKjUfU9wKNFO6N1wRVacOw

 

Marina

 

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4 Replies
Visitor marinamarti
Visitor
83 Views
Registered: ‎05-12-2019

Re: vivado is removing usefull "logic" (all the design)

MIPS.JPG

I post this schematic of the microprocessor MIPS design, my design contents more signals because I have made this design bigger in order to support more instructions, but more or less follows this one, just for you to have an idea. Thank you so much! I have to solve the issue because it is an important project for the university! 

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Scholar u4223374
Scholar
76 Views
Registered: ‎04-26-2015

Re: vivado is removing usefull "logic" (all the design)

Normally, when Vivado is removing all the logic, it's because it has decided that all outputs have constant values that can be determined during synthesis. Obviously in this case there's no point including a lot of logic to generate them, so Vivado helpfully optimizes that logic out of the design.

 

So, based on that:

- Does your design actually have user-accessible outputs (ie going out to pins)?

- Does your design have inputs? Obviously a design with no inputs is not going to have changing outputs, unless you've constructed a ring oscillator.

Visitor marinamarti
Visitor
69 Views
Registered: ‎05-12-2019

Re: vivado is removing usefull "logic" (all the design)

The design has inputs (the switches of the board) and outputs (the vector exceptions and another output that goes to the LEDS of the board.

At the INSTRUCTION MEMORY is where it has de program to be executed, and depending on the instruction that is reading from the INSTRUCTION MEMORY, it will set the control signals that this instruction requires.

For the moment I have putted a little program at the INSTRUCTION MEMORY that is basically an infinite loop that reads position 0 and 1 of the DATA MEMORY (where are the input of the switches), adds this two values and stores the result at position 3 of the DATA MEMORY (that is the output that goes to the leds of the board).

I've thought that maybe it's removing the instruction memory because it's so large (1024x32) and it is almost full of zeros, because the little program of the infinite loop only occups 6 positions of the 1024 that it has. Is this possible? Or it might be removing logic for another reason? (notice that if it removes the INSTRUCTION MEMORY the microprocessor has no instruction to execute so all signals go to '0', so this removal is a big problem).

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Xilinx Employee
Xilinx Employee
27 Views
Registered: ‎05-14-2008

Re: vivado is removing usefull "logic" (all the design)

You can set submodules as top level one by one and run synthesis.

And see if the logics are removed.

This will give you a clue which module causes the trimming of logics.

-vivian

 

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