01-20-2019 06:25 AM
reg [3:0] curr_s; //FSM current state reg [3:0] next_s; //FSM next state always @(posedge clk_r or negedge rst_n) begin if(!rst_n) curr_s <= idle_s; else begin curr_s <= next_s; end end // FSM second level always @(*) begin case (curr_s) idle_s : begin if( PS2PL_signal[2:0] == 3'b001 ) next_s = load_BN_s; // waring inferring latch else if( PS2PL_signal[2:0] == 3'b010 ) next_s = load_WF_s; else next_s = idle_s; end load_BN_s : begin if( loadBN_cnt == ParaLoadBN ) next_s = load_WF_s; else next_s = load_BN_s; end load_WF_s : begin if( loadWF_cnt == ParaLoadWF ) next_s = calc_AB_s; else next_s = load_WF_s; end calc_AB_s : begin if( DMA_cnt < ParaAllOutMapDMA && conv_cnt == ParaCNNCalc ) next_s = calc_BA_s; else if( DMA_cnt == ParaAllOutMapDMA && conv_cnt == ParaCNNCalc) next_s = idle_s; else next_s = calc_AB_s; end calc_BA_s : begin if( DMA_cnt < ParaAllOutMapDMA && conv_cnt == ParaCNNCalc ) next_s = calc_AB_s; else if( DMA_cnt == ParaAllOutMapDMA && conv_cnt == ParaCNNCalc) next_s = idle_s; else next_s = calc_BA_s; end default next_s <= idle_s; endcase end
01-20-2019 06:35 AM
01-20-2019 06:45 AM
01-22-2019 10:51 AM
I can't spot the latch - you look to have all conditions covered. In any event, a catch-all solution to this is to always assign a "default" assignment near the beginning of your combinational procedural block
// FSM second level always @(*) begin next_s = curr_s; // Or some other "default" assignment -this "default" means when all else fails, stay in the same state. // add other state machine output "default" outputs here too case (curr_s) ...
This suggestions is an alternative to drjohnsmith's suggestions of recoding as one always block.
05-12-2019 10:27 PM
Hi @pclet ,
You are asking a question on an old thread.
Please create a fresh new thread with your queries in detail and community will help you out asap.