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yinbinjun
Visitor
Visitor
3,278 Views
Registered: ‎12-10-2018

waring [Synth 8-327] inferring latch for variable 'next_s_reg'

reg   [3:0]     curr_s;        		//FSM current state
reg   [3:0]     next_s;        		//FSM next state

always @(posedge clk_r or negedge rst_n)
begin
    if(!rst_n)
        curr_s <= idle_s;
    else  begin 
        curr_s <= next_s;
    end
end
// FSM second level
always @(*)
begin
    case (curr_s)
            idle_s    : begin
                        if( PS2PL_signal[2:0] == 3'b001 )	
                            next_s = load_BN_s; // waring inferring latch
                        else if( PS2PL_signal[2:0] == 3'b010 )
                            next_s = load_WF_s;
                        else next_s = idle_s; 					
                    end
            load_BN_s : begin 
                        if( loadBN_cnt == ParaLoadBN )  
                            next_s = load_WF_s;
                        else next_s = load_BN_s;         							
                    end	
            load_WF_s : begin 
                         if( loadWF_cnt == ParaLoadWF ) 
                             next_s = calc_AB_s;
                         else next_s = load_WF_s;                                     
                    end          			
            calc_AB_s : begin
			 if( DMA_cnt < ParaAllOutMapDMA && conv_cnt == ParaCNNCalc )
				next_s = calc_BA_s;
                         else if( DMA_cnt == ParaAllOutMapDMA && conv_cnt == ParaCNNCalc) 
				next_s = idle_s;
			 else next_s = calc_AB_s;      
                    end 
            calc_BA_s : begin 
			 if( DMA_cnt < ParaAllOutMapDMA && conv_cnt == ParaCNNCalc )
				next_s = calc_AB_s;
                         else if( DMA_cnt == ParaAllOutMapDMA && conv_cnt == ParaCNNCalc) 
				next_s = idle_s;
			 else next_s = calc_BA_s;                          
                    end	
        default   next_s <= idle_s;
    endcase		
end		

 

 

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8 Replies
drjohnsmith
Teacher
Teacher
3,266 Views
Registered: ‎07-09-2009

try defining defining state machines as a single item, not a clocked and a none clocked process,
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yinbinjun
Visitor
Visitor
3,263 Views
Registered: ‎12-10-2018

you mean that I need to split the state machine?

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yinbinjun
Visitor
Visitor
3,260 Views
Registered: ‎12-10-2018

you mean that I need to split the state machine?
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drjohnsmith
Teacher
Teacher
3,256 Views
Registered: ‎07-09-2009

the opposite, you currently have to parts, the clocked and the un clocked process,
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markcurry
Scholar
Scholar
3,179 Views
Registered: ‎09-16-2009

I can't spot the latch - you look to have all conditions covered.  In any event, a catch-all solution to this is to always assign a "default" assignment near the beginning of your combinational procedural block 

// FSM second level
always @(*)
begin
   next_s = curr_s;  // Or some other "default" assignment -this "default" means when all else fails, stay in the same state.
   // add other state machine output "default" outputs here too 
   case (curr_s)
...

 

This suggestions is an alternative to drjohnsmith's suggestions of recoding as one always block.

Regards,

Mark

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yinbinjun
Visitor
Visitor
3,164 Views
Registered: ‎12-10-2018

I have solved this problem
change
default next_s <= idle_s;
pclet
Visitor
Visitor
2,830 Views
Registered: ‎01-27-2011

Hi

It's issued my code.

I don't understand your solution.

Please explain more specifically. 

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hemangd
Moderator
Moderator
2,807 Views
Registered: ‎03-16-2017

Hi @pclet , 

You are asking a question on an old thread.

Please create a fresh new thread with your queries in detail and community will help you out asap.

Regards,
hemangd

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