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851 Views
Registered: ‎05-11-2018

270MHz possible on an FPGA?

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Hi,

 

I am trying to close timing on a design which has 19% utilization on a Virtex US+ FPGA. Is this a decent enough clock frequency to try to meet timing. Or am I being very optimistic to close timing at this frequency? I know the utilization is low, but seems like I have major timing closure issues even after using various implementation strategies i.e Phy_opt_Design(PerformanceExplore_routing), P_blocks on modules with this frequency etc.

 

Any pointers would be really helpful.

 

Thanks,

Anirudh

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avrumw
Guide
Guide
877 Views
Registered: ‎01-23-2009

This depends greatly on how the RTL is coded.

 

If the design is coded for high clock frequency (ensuring that the combinatorial complexity between flip-flops is very low), then you can reach speeds of over 500MHz - maybe even more in an US+. Conversely, if your code has lots of combinatorial logic between flip-flop stages, it can be challenging to meet timing at 100MHz (or even lower).

 

So the question is asked somewhat backwards...

 

Is it possible - even reasonable - to try and design something to run at 270MHz in an UltraScale+ (or even a Kintex-7) - absolutely. But with that as a goal, you need to code in a way that makes it possible...

 

Avrum

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2 Replies
bruce_karaffa
Scholar
Scholar
818 Views
Registered: ‎06-21-2017

27- MHz with a Virtex US+ should not be difficult.  Is your problem with the IO portion of your design or deeper into the processing?  If not IO, some other possibilities are improper clock domain crossings, too many levels of logic between registers or very deeply cascaded BRAM.  Can you supply more info about your design and attach a timing report?

avrumw
Guide
Guide
878 Views
Registered: ‎01-23-2009

This depends greatly on how the RTL is coded.

 

If the design is coded for high clock frequency (ensuring that the combinatorial complexity between flip-flops is very low), then you can reach speeds of over 500MHz - maybe even more in an US+. Conversely, if your code has lots of combinatorial logic between flip-flop stages, it can be challenging to meet timing at 100MHz (or even lower).

 

So the question is asked somewhat backwards...

 

Is it possible - even reasonable - to try and design something to run at 270MHz in an UltraScale+ (or even a Kintex-7) - absolutely. But with that as a goal, you need to code in a way that makes it possible...

 

Avrum

View solution in original post