About Timing errors in Post route simulation in modelsim

[samuel.gaowen@gmail]

Dear,

I have written a project for Xilinx's NetFPGA board, and my project works fine in behavorial simulation but got errors in post route simulation.
The output is always the combination of "XXXXX" and "0000".The pictures of my post_route_simulation and behavorial sim are as attachment.

I found the static timing report says that nearly all my clks are FALSE clock as follows:

Setup/Hold to clock in_wr_c
-------------+------------+------------+----------------------------------------------+--------+
             |  Setup to  |  Hold to   |                                              | Clock  |
Source       | clk (edge) | clk (edge) |Internal Clock(s)                             | Phase  |
-------------+------------+------------+----------------------------------------------+--------+
in_data_c<0> |    1.317(F)|   -0.188(F)|in_wr_c_BUFGP                                 |   0.000|
             |    0.706(F)|    4.812(F)|pkt_analysis_decoder_c/hdr_b_clk_cycle_not0001|   0.000|
in_data_c<1> |    1.490(F)|   -0.326(F)|in_wr_c_BUFGP                                 |   0.000|
             |    0.330(F)|    5.063(F)|pkt_analysis_decoder_c/hdr_b_clk_cycle_not0001|   0.000|
in_data_c<2> |    0.662(F)|    0.348(F)|in_wr_c_BUFGP                                 |   0.000|
             |    1.033(F)|    4.545(F)|pkt_analysis_decoder_c/hdr_b_clk_cycle_not0001|   0.000|
in_data_c<3> |    0.555(F)|    0.436(F)|in_wr_c_BUFGP                                 |   0.000|
             |    0.607(F)|    4.799(F)|pkt_analysis_decoder_c/hdr_b_clk_cycle_not0001|   0.000|
Post route simulation Errors are as follows:

# ** Error: I:/Xilinx/verilog/mti_se/simprims_ver/simprims_ver_source.v(23270): $hold( negedge CLK:304273 ps, negedge I &&& in_clk_enable1:304323 ps, 168 ps );
#    Time: 304323 ps  Iteration: 0  Instance: /test_decoder_top/test_decoder/\pkt_make/hdr_clk_cycle_0\
# ** Error: I:/Xilinx/verilog/mti_se/simprims_ver/simprims_ver_source.v(23270): $hold( negedge CLK:305111 ps, negedge I &&& in_clk_enable1:305152 ps, 168 ps );
#    Time: 305152 ps  Iteration: 0  Instance: /test_decoder_top/test_decoder/\decoder_NC/data_b_clk_cycle_3\
# ** Error: I:/Xilinx/verilog/mti_se/simprims_ver/simprims_ver_source.v(23270): $hold( negedge CLK:305111 ps, negedge I &&& in_clk_enable1:305165 ps, 168 ps );
#    Time: 305165 ps  Iteration: 0  Instance: /test_decoder_top/test_decoder/\decoder_NC/data_b_clk_cycle_2\

I have  no idea how I can solve this problem, just do not know whether this problem is resulting from the design or a timing issue.

I saw an answer here that "to remove the file containing the timing delays (often the SDF file) from the post-route simulation.  In effect, you will be performing a post-route, gate level  simulation without any timing information. "at http://forums.xilinx.com/xlnx/board/message?board.id=TIMEANBD&thread.id=735

As above says, I tried to remove the sdf file in "netgen/par" for my top module, but found that the ISE just regenerate a new SDF file same to the prior one. Therefore I could not know whether it is functional problems.

Part of my codes are as follows:

         always @(*) begin

                case(state)

        /*Get hdr_b and output it*/
          HEADR_B: begin
             if(in_wr) begin
                 out_pkt_hdr  = in_data;
                 out_ctrl_hdr=8'hff;
                 out_wr_hdr=1;
                 length_hdr_b = in_data[15:0]-length_data_b+8;//get length of header_b,including b's module hdr.
                  hdr_b_clk_cycle = (length_hdr_b>>3)-1; // calculate clk cycle of hdr_b
                  
                  state_next = WAIT_DATA_B;
              end
          end  
          WAIT_EOP: begin//EOP
             if(in_ctrl == 0 && in_wr)begin
                   rdy_syn=1;
                   out_ctrl=8'h00;
                   out_wr=1;
                   out_pkt_data        = in_data;
              end
             else if(in_ctrl !=0 && in_wr) begin
                      out_pkt_data        = in_data;
                      out_ctrl=in_ctrl;
                      out_wr=1;
                      state_next = MODULE_HDR;
              end
        end//wait_eop
          
      endcase // case(state)

end

Is there a better way to modify the codes but not cause so much work, because the deadline of the project is urgent and I used this coding pattern in most of my modules. Is it true that the system could not work fine if it could not pass through post route simulation?

 Thanks in advance for any advice!

Message Edited by samuel.gaowen@gmail on 03-24-2010 11:03 PM

Message Edited by samuel.gaowen@gmail on 03-25-2010 04:00 AM

Message Edited by samuel.gaowen@gmail on 03-25-2010 05:49 AM

[samuel.gaowen@gmail]

the right output(out_data,out_ctrl,out_wr) is as behavorial simulation.

behavorial simulation is as following picture.

[hobson]

Samuel,

First of all, the (F) notation in the static timing report indicates that the clock is capturing the data on the falling clock edge, not that it's a false clock.

Second, have you properly constrained the design by putting PERIOD, OFFSET, and other constraints in your UCF file?  If so, does the static timing report indicate that these constraints have been met?

In general, if a design simulates correctly in behavioral simulation, but not in post-route timing simulation, the problem is timing rather than functional. Note that I said that this is generally the case, but it's not absolutely always true. To collect more evidence on whether this is a functional or timing issue, you may wish to run a post-synthesis or post-Translate simulation.  If these simulations work, then the problem is almost certainly a timing problem.

By the way, if you want to remove the SDF file, you will probably have to run the simulation natively in Modelsim and modify the scripts rather than launching it via ISE.  ISE will overwrite the scripts every time you click on "Simulate Post-Place and Route...", so be careful.

Anyway, more important than doing those simulations, I think you should focus on your timing constraints, ensuring that they cover all the paths you intend them to cover, and analyze what paths, if any, are failing to meet the timing constraints.

Regards,

-Hobson

[samuel.gaowen@gmail]

Dear Hobson,

Thank you so much for your concern and your suggestions are truly helpful.

I tried post translate and post map simulation, which is still not correct(just combination of "XXXX" and "0000").  So  is it proabably a  functional problem?

I am not familiar with timing constraints at all, so would you mind if you could give me any instructions? I was informed that changing timing constraints is so hard, which takes a very long time and needs enough experience. However, I just do not have enough time(less than 2 days). I also tried to write my own constraints, but fail to accomplish it after hours' work. During the STA analysis I found the delay in a module takes almost half of the clk cycle. 

So I began to modify my source code in order to add a new level of pipeline to reduce the complexity in my code, such as add a new module to  reduce the complexity of my code in a module.  Am I in the right way? Could you give me more instructions?

Thank you again!

Regards,

Samuel

Message Edited by samuel.gaowen@gmail on 03-25-2010 09:05 PM

[samuel.gaowen@gmail]

My full static timing report is as this, Is it true that the setup time for a input signal is  too long to be met? The clock cycle time is only 8ns. Is it possible that I count write timing constraints for one of following signal to let the signal have enough time.  How could I do this? any ideas?

Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
in_ctrl_a<0>|    2.611(R)|   -1.044(R)|clk_BUFGP         |   0.000|
in_ctrl_a<1>|    2.172(R)|   -0.378(R)|clk_BUFGP         |   0.000|
in_ctrl_a<2>|    2.102(R)|   -0.475(R)|clk_BUFGP         |   0.000|
in_ctrl_a<3>|    2.450(R)|   -0.632(R)|clk_BUFGP         |   0.000|
in_ctrl_a<4>|    2.540(R)|   -0.777(R)|clk_BUFGP         |   0.000|
in_ctrl_a<5>|    2.752(R)|   -0.503(R)|clk_BUFGP         |   0.000|
in_ctrl_a<6>|    2.654(R)|   -0.913(R)|clk_BUFGP         |   0.000|
in_ctrl_a<7>|    2.637(R)|   -0.769(R)|clk_BUFGP         |   0.000|
in_ctrl_c<0>|    4.711(R)|   -1.226(R)|clk_BUFGP         |   0.000|
in_ctrl_c<1>|    4.582(R)|   -1.175(R)|clk_BUFGP         |   0.000|
in_ctrl_c<2>|    4.519(R)|   -1.124(R)|clk_BUFGP         |   0.000|
in_ctrl_c<3>|    4.799(R)|   -1.207(R)|clk_BUFGP         |   0.000|
in_ctrl_c<4>|    3.642(R)|   -1.355(R)|clk_BUFGP         |   0.000|
in_ctrl_c<5>|    3.660(R)|   -1.388(R)|clk_BUFGP         |   0.000|
in_ctrl_c<6>|    3.357(R)|   -1.133(R)|clk_BUFGP         |   0.000|
in_ctrl_c<7>|    3.415(R)|   -1.167(R)|clk_BUFGP         |   0.000|
reset       |    3.991(R)|   -1.479(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock in_wr_c
-------------+------------+------------+----------------------------------------------+--------+
             |  Setup to  |  Hold to   |                                              | Clock  |
Source       | clk (edge) | clk (edge) |Internal Clock(s)                             | Phase  |
-------------+------------+------------+----------------------------------------------+--------+
in_data_c<0> |    0.790(F)|    0.212(F)|in_wr_c_BUFGP                                 |   0.000|
             |    1.064(F)|    3.966(F)|pkt_analysis_decoder_c/hdr_b_clk_cycle_not0001|   0.000|
in_data_c<1> |    0.678(F)|    0.304(F)|in_wr_c_BUFGP                                 |   0.000|
             |    1.272(F)|    3.751(F)|pkt_analysis_decoder_c/hdr_b_clk_cycle_not0001|   0.000|
in_data_c<2> |    0.897(F)|    0.127(F)|in_wr_c_BUFGP                                 |   0.000|
             |    1.227(F)|    3.838(F)|pkt_analysis_decoder_c/hdr_b_clk_cycle_not0001|   0.000|
in_data_c<3> |    0.860(F)|    0.151(F)|in_wr_c_BUFGP                                 |   0.000|
             |    0.588(F)|    4.293(F)|pkt_analysis_decoder_c/hdr_b_clk_cycle_not0001|   0.000|
in_data_c<4> |    0.605(F)|    0.372(F)|in_wr_c_BUFGP                                 |   0.000|
             |   -0.107(F)|    3.509(F)|pkt_analysis_decoder_c/hdr_b_clk_cycle_not0001|   0.000|
in_data_c<5> |    0.691(F)|    0.308(F)|in_wr_c_BUFGP                                 |   0.000|
             |   -0.352(F)|    3.291(F)|pkt_analysis_decoder_c/hdr_b_clk_cycle_not0001|   0.000|
in_data_c<6> |    0.649(F)|    0.353(F)|in_wr_c_BUFGP                                 |   0.000|
             |   -1.231(F)|    3.587(F)|pkt_analysis_decoder_c/hdr_b_clk_cycle_not0001|   0.000|
in_data_c<7> |    0.820(F)|    0.215(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<8> |    1.173(F)|   -0.148(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<9> |    1.296(F)|   -0.248(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<10>|    0.822(F)|    0.157(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<11>|    0.899(F)|    0.095(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<12>|    0.324(F)|    0.599(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<13>|    0.577(F)|    0.399(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<14>|    0.429(F)|    0.518(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<15>|    0.578(F)|    0.408(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<16>|    1.093(F)|   -0.030(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<17>|    1.225(F)|   -0.129(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<18>|    0.275(F)|    0.640(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<19>|    0.221(F)|    0.682(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<20>|    0.281(F)|    0.592(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<21>|    0.223(F)|    0.638(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<22>|    1.886(F)|   -0.696(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<23>|    1.907(F)|   -0.703(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<24>|    1.686(F)|   -0.548(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<25>|    1.718(F)|   -0.572(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<26>|    0.459(F)|    0.484(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<27>|    0.383(F)|    0.543(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<28>|    0.362(F)|    0.574(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<29>|    0.242(F)|    0.671(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<30>|    1.412(F)|   -0.303(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<31>|    1.422(F)|   -0.311(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<32>|    0.357(F)|    0.564(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<33>|    0.121(F)|    0.755(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<34>|    0.598(F)|    0.381(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<35>|    0.592(F)|    0.383(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<36>|    0.595(F)|    0.378(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<37>|    0.401(F)|    0.533(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<38>|    0.290(F)|    0.626(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<39>|    0.398(F)|    0.537(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<40>|    0.532(F)|    0.427(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<41>|    0.569(F)|    0.401(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<42>|    0.196(F)|    0.711(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<43>|    0.013(F)|    0.857(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<44>|    0.314(F)|    0.609(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<45>|    0.138(F)|    0.752(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<46>|    0.349(F)|    0.577(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<47>|    0.475(F)|    0.474(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<48>|    0.957(F)|    0.066(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<49>|    0.854(F)|    0.145(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<50>|    0.595(F)|    0.383(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<51>|    0.711(F)|    0.289(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<52>|    0.907(F)|    0.137(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<53>|    0.711(F)|    0.287(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<54>|    0.209(F)|    0.672(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<55>|    0.229(F)|    0.656(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<56>|    0.951(F)|    0.083(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<57>|    0.752(F)|    0.242(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<58>|    0.715(F)|    0.263(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<59>|    0.584(F)|    0.365(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<60>|   -0.066(F)|    0.885(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<61>|   -0.156(F)|    0.958(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<62>|    0.560(F)|    0.366(F)|in_wr_c_BUFGP                                 |   0.000|
in_data_c<63>|    0.381(F)|    0.510(F)|in_wr_c_BUFGP                                 |   0.000|
-------------+------------+------------+----------------------------------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
out_wr      |   13.722(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock in_wr_c to Pad
--------------+------------+-------------------------+--------+
              | clk (edge) |                         | Clock  |
Destination   |   to PAD   |Internal Clock(s)        | Phase  |
--------------+------------+-------------------------+--------+
out_ctrl<0>   |   14.936(F)|pkt_make/out_ctrl_not0001|   0.000|
out_ctrl<1>   |   14.927(F)|pkt_make/out_ctrl_not0001|   0.000|
out_ctrl<2>   |   14.939(F)|pkt_make/out_ctrl_not0001|   0.000|
out_ctrl<3>   |   14.928(F)|pkt_make/out_ctrl_not0001|   0.000|
out_ctrl<4>   |   14.933(F)|pkt_make/out_ctrl_not0001|   0.000|
out_ctrl<5>   |   14.932(F)|pkt_make/out_ctrl_not0001|   0.000|
out_ctrl<6>   |   14.938(F)|pkt_make/out_ctrl_not0001|   0.000|
out_ctrl<7>   |   14.941(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<0> |   14.760(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<1> |   14.758(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<2> |   14.717(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<3> |   14.722(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<4> |   14.720(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<5> |   14.698(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<6> |   14.810(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<7> |   14.825(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<8> |   14.724(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<9> |   14.760(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<10>|   14.633(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<11>|   14.631(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<12>|   14.692(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<13>|   14.631(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<14>|   14.805(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<15>|   14.849(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<16>|   14.698(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<17>|   14.622(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<18>|   14.708(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<19>|   14.689(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<20>|   14.796(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<21>|   14.693(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<22>|   14.708(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<23>|   14.706(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<24>|   14.641(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<25>|   14.801(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<26>|   14.640(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<27>|   14.618(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<28>|   14.837(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<29>|   14.797(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<30>|   14.643(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<31>|   14.699(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<32>|   14.715(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<33>|   14.720(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<34>|   14.812(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<35>|   14.796(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<36>|   14.690(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<37>|   14.739(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<38>|   14.718(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<39>|   14.713(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<40>|   14.697(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<41>|   14.709(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<42>|   14.812(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<43>|   14.801(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<44>|   14.823(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<45>|   14.818(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<46>|   14.736(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<47>|   14.727(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<48>|   14.745(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<49>|   14.748(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<50>|   14.633(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<51>|   14.643(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<52>|   14.713(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<53>|   14.731(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<54>|   14.721(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<55>|   14.712(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<56>|   14.816(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<57>|   14.752(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<58>|   14.740(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<59>|   14.739(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<60>|   14.804(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<61>|   14.759(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<62>|   14.756(F)|pkt_make/out_ctrl_not0001|   0.000|
out_data_b<63>|   14.795(F)|pkt_make/out_ctrl_not0001|   0.000|
--------------+------------+-------------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    5.069|         |         |         |
in_wr_a        |    6.054|    6.054|         |         |
in_wr_c        |    7.819|    7.819|         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock in_wr_a
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |         |         |    3.161|         |
in_wr_a        |         |         |    1.420|    1.453|
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock in_wr_c
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |         |         |   11.817|         |
in_wr_c        |         |         |    6.729|   10.779|
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
in_wr_c        |out_wr         |   16.245|
---------------+---------------+---------+

[roym · Accepted solution]

Hi,

Initialize your inputs to 0 (or some reasonable value) at the very start of your simulation.  Watch out for case statements without a default branch.  The combination of undefinded inputs and undefined states can get your design "lost".

Good luck,

Roy

[samuel.gaowen@gmail]

Dear Roy,

Thank you again for your careful consideration and help!

Regards,

Samuel