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Explorer
Explorer
333 Views
Registered: ‎06-08-2017

Adjust timing of clock and data from an external chip

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I've got a chip that sends 24 bit data packets at up to 100 MHz.

At 50 MHz, the data downloads to the FPGA with no errors.

At 100 MHz it appears the data edge is close to the clock edge.

Is there a way to adjust the timing between the clock and data? I've tried adjusting the min/max input_delays, and seen no change. Does this mean my constraints are wrong?

Thank you.

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1 Solution

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Guide avrumw
Guide
307 Views
Registered: ‎01-23-2009

Re: Adjust timing of clock and data from an external chip

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Generally I/O interfaces use either the IOB flip-flop or the ISERDES. Both of these resources are "fixed" (there is no variable routing), so assuming you are using a normal clock scheme, there is nothing the tools can do to adjust the clock/data phase relationship. Consequently, the set_input_delay and set_output_delay only provide information for verifying that your interface will work.

So, first, start the other way. Your constraints must be extracted from the device sending the data.

Next, choose a proper clocking scheme and a mechanism for adjusting the clock/data phase relationship. The referenced post talks about adjusting the clock/data phase relationship using either the IDELAY or the MMCM phase adjustment. Both of these mechanisms have to be instantiated and tuned manually - for the MMCM you need to specify the clock phase, and for the IDELAY you need to specify the number of taps you want to use. Once this is done, the timing analysis will accurately reflect the timing of the interface including these programmed delays/phases. But, again, in order for this to provide any meaningful information, you need complete and correct timing constraints extracted from the datasheet of the device you are communicating with.

Avrum

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2 Replies
Guide avrumw
Guide
308 Views
Registered: ‎01-23-2009

Re: Adjust timing of clock and data from an external chip

Jump to solution

Generally I/O interfaces use either the IOB flip-flop or the ISERDES. Both of these resources are "fixed" (there is no variable routing), so assuming you are using a normal clock scheme, there is nothing the tools can do to adjust the clock/data phase relationship. Consequently, the set_input_delay and set_output_delay only provide information for verifying that your interface will work.

So, first, start the other way. Your constraints must be extracted from the device sending the data.

Next, choose a proper clocking scheme and a mechanism for adjusting the clock/data phase relationship. The referenced post talks about adjusting the clock/data phase relationship using either the IDELAY or the MMCM phase adjustment. Both of these mechanisms have to be instantiated and tuned manually - for the MMCM you need to specify the clock phase, and for the IDELAY you need to specify the number of taps you want to use. Once this is done, the timing analysis will accurately reflect the timing of the interface including these programmed delays/phases. But, again, in order for this to provide any meaningful information, you need complete and correct timing constraints extracted from the datasheet of the device you are communicating with.

Avrum

View solution in original post

Explorer
Explorer
248 Views
Registered: ‎06-08-2017

Re: Adjust timing of clock and data from an external chip

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Capturing the incoming data on a phase shifted clock worked. I knew I had to do something like this. At first I was trying to adjust the phase of the outgoing clock (the clock that went to the ADC), rather than using a separate phase shifted clock just to capture the data coming into the FPGA from the ADC. I realize now the my first idea does not make sense.

Thanks for the help!
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