04-22-2019 06:18 AM
Hello, previous posting on synthesis.
After PNR, bitstream generated, but, RUN then FPGA shutdown/reset.
Also, there's Design timing issues. here's snapshot of fault.
It is run on 350Mhz core clock.
How can I resolve it , with incremental way? (for save a pnr time).
04-22-2019 06:29 AM
Also , Power Consume estimation is high, more higher value is TEMP.
Never over 90C.
04-22-2019 06:47 AM - edited 04-22-2019 06:47 AM
Is it help? on UG949 page 240~ . block retiming strategy?
or is there carry optimization options , when Implentation?
04-22-2019 06:47 AM
I recommend that you check out the Xilinx "UltraFast Design Methodology":
Lots of good information on proper design techniques and timing analysis. When designing for clock rates in the 350 MHz range, it is very important to follow all of the recommendations in order to meet timing. Proper design will also improve the power consumption.
04-22-2019 06:52 AM
04-22-2019 07:12 AM
ok thanks for advices.
we already did 500Mhz , 96% LUT fit, with PCI-e.
Now, we are doing another algorithm, so, there's multiple view of digging.
one of paths rewrite code,
one of paths case by case treat to run, I need to handle xilinx tool option and handy treatment for Ultrafast workaround.
Is there any option for trial?
thanks, in advance.
04-22-2019 09:32 PM
Hi @trustfarm ,
Provide full timing summary report by running report_timing_summary after implementation to evaluate.
04-22-2019 10:04 PM