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zvigol
Visitor
Visitor
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Registered: ‎12-01-2016

Analyzing Intermediate Timing Summary

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Hello

Is there a way to identify and analyze problematic timing paths during routing phase ?

I get message like : Intermediate Timing Summary | WNS=0.238 | TNS=0.000 | WHS=-0.279 | THS=-19.724| 

But what are the problematic paths ? 

Thanks

Zvi Goldenberg

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zvigol
Visitor
Visitor
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Registered: ‎12-01-2016

That's my usual methodology . I was wondering if I can accelerate design analysis and understanding

Thanks

Zvi

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hongh
Moderator
Moderator
379 Views
Registered: ‎11-04-2010

It's recommended to the analyze the timing result of the final routed dcp. To avoid the hold violation, please try to check the result of report_clock_interaction first.

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zvigol
Visitor
Visitor
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Registered: ‎12-01-2016

Hello

I do these recommended actions regularly .

However , I am wondering if I can predict the problematic paths meanwhile during routing phase.

Maybe tool is working hard for non-real path ?

 

Thanks

Zvi

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dpaul24
Scholar
Scholar
302 Views
Registered: ‎08-07-2014

@zvigol ,

However , I am wondering if I can predict the problematic paths meanwhile during routing phase.

Let the tool do it, believe me, it is very good at it!

What you can ensure at your end before synthesis is a correctly and properly written HDL and fully constrained design. Given these two criterion and assuming that the FPGA has about 20% free space, the tool will come up with best routing.

------------FPGA enthusiast------------
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zvigol
Visitor
Visitor
295 Views
Registered: ‎12-01-2016

That's my usual methodology . I was wondering if I can accelerate design analysis and understanding

Thanks

Zvi

View solution in original post

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