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ivan.mironenko
Contributor
Contributor
12,444 Views
Registered: ‎09-10-2008

Any experience with Spartan-3A IDDR2 component and OFFSET IN constraints?

Hi,
I am trying to constrain the inputs of the LVDS deserializer with OFFSET IN constraint, and it just seems that it is not possible, or I am missing something.

 

1) I have tried to create the constraints by using "Create Timing Constraints" master in ISE, which  actually has presets for "DDR center aligned" OFFSET IN constraints.
2) I have read WP237: "What are OFFSET Constraints?" and tried to use the constraints from Dual-Data Rate Example on page.13.
3) I have also tried to invent my own way to separate FFs clocked by rising or falling edge, tried to apply the constraints to different INST, FFS,BELs etc etc etc., all without luck.

I think that the problems I have have something to do with IDDR2 component which I am using to reclock the DDR data,  but of course I am not sure.

Has anybody successfully used OFFSET IN constraints in combination with Spartan-3A IDDR2 components?
Or is there another way to control Tsetup/Thold for the DDR input registers?

What makes me even more suspicious is that all reference designs I have seen which implement high speed DDR SERDES (For example, XAPP774 "Connecting Xilinx FPGAs to Texas Instruments ADS527x Series ADCs", or XAPP866)
 do not have any OFFSET IN constraints in ucf.
 
 They use MAXDELAY or NODELAY, or DELAY_ADJUSTsomething on the input nets and I am lead to believe that it is supposed to work OK,but is it so?
 These constraints might work at the beginning if you "tune" them, but then, as design grows, the clock skew and routing will change and these
 static constraints will not be of any help, because the Tsetup and Thold for FFs in IOB are still unconstrained.
 Is it so or am I wrong?

 


OK,here is approximately  what I am trying to do. For the test purposes I have reduced my design to the bare minimum:

The top module has one IBUFDS for data, one IBUFDS for clock,  an IDDR2 component, and a DCM with some buffers in the feedback


entity top is
    Port ( dco_p   : in  STD_LOGIC;                       -- Clock
           dco_n   : in  STD_LOGIC;                        
           ch_p    : in  STD_LOGIC;                       -- Data in
           ch_n    : in  STD_LOGIC;
           par_out : out  STD_LOGIC_VECTOR (1 downto 0)); -- Data out
end top;
architecture Behavioral of top is

 

-- Clocks
signal ClkToDCM       :     std_logic;
signal ClkDCMtoBUF0   :     std_logic;
signal ClkDCMtoBUF180 :     std_logic;
signal IntRxClk       :    std_logic;
signal IntRxClkNot    :    std_logic;

--Data
signal ch_int         :     std_logic;
signal ch_int_p       :     std_logic;
signal ch_int_n       :     std_logic;

begin
  CLKIN_IBUFGDS_INST :IBUFGDS port map (I => dco_p,IB => dco_n, O => ClkToDCM);
  DATAIN_IBUFDS_INST :IBUFDS  generic map (DIFF_TERM => TRUE)
                              port map (I => ch_p,IB => ch_n, O => ch_int);
                             
IDDR2_INST: IDDR2 generic map(DDR_ALIGNMENT => "C0",INIT_Q0 => '0',INIT_Q1 => '0',SRTYPE => "SYNC")
                  port map (Q0 => ch_int_p,    -- 1-bit output captured with C0 clock
                            Q1 => ch_int_n,    -- 1-bit output captured with C1 clock
                            C0 => IntRxClk,    -- 1-bit clock input
                            C1 => IntRxClkNot, -- 1-bit clock input
                            CE => '1',         -- 1-bit clock enable input
                            D  => ch_int,      -- 1-bit data input
                            R  => '0',         -- 1-bit reset input
                            S  => '0'          -- 1-bit set input

                  );
par_out <= ch_int_p & ch_int_n;


CLK0_BUFG_INST : BUFG port map (I=>ClkDCMtoBUF0,O=>IntRxClk);
   CLK180_BUFG_INST : BUFG port map (I=>ClkDCMtoBUF180,O=>IntRxClkNot);
   DCM_SP_INST : DCM_SP
   generic map( CLK_FEEDBACK => "1X",
            CLKIN_DIVIDE_BY_2 => FALSE,
            CLKIN_PERIOD => 3.57,
            CLKOUT_PHASE_SHIFT => "NONE",
            DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
            DUTY_CYCLE_CORRECTION => TRUE,
            FACTORY_JF => x"C080",
            PHASE_SHIFT => 0,
            STARTUP_WAIT => FALSE)
      port map (CLKFB=> IntRxClk,
                CLKIN=>ClkToDCM,
                DSSEN=>'0',
                PSCLK=>'0',
                PSEN=>'0',
                PSINCDEC=>'0',
                RST=>'0',
                CLKDV=>open,
                CLKFX=>open,
                CLKFX180=>open,
                CLK0=>ClkDCMtoBUF0,
                CLK2X=>open,
                CLK2X180=>open,
                CLK90=>open,
                CLK180=>ClkDCMtoBUF180,
                CLK270=>open,
                LOCKED=>open,
                PSDONE=>open,
                STATUS(7 downto 0)=>open);
                                                               
end Behavioral;


And the timing constraints are:


TIMESPEC TS_dco_n = PERIOD "dco_n" 250 MHz HIGH 50%;
OFFSET = IN 1 ns VALID 2 ns BEFORE dco_n RISING;
OFFSET = IN 1 ns VALID 2 ns BEFORE dco_n FALLING;



Does anybody has an idea what is wrong with my constraints?

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17 Replies
Anonymous
Not applicable
12,425 Views

When you define the period and offset constraints, why not use the P side port as the reference pin?

What kind of errors you have seen?

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ivan.mironenko
Contributor
Contributor
12,418 Views
Registered: ‎09-10-2008

Hi,

I have tried both DCO_P and DCO_N, the results are the same. 

 

Oh I forgot to mention the errors.

 

First there are two interesting warnings:

 

WARNING:Timing:3224 - The clock dco_p associated with OFFSET = IN 1 ns VALID 2 ns BEFORE COMP "dco_p" "FALLING"; does
   not clock any registered input components.
WARNING:Timing:3225 - Timing constraint OFFSET = IN 1 ns VALID 2 ns BEFORE COMP "dco_p" "FALLING"; ignored during timing
   analysis

 

And then there is one failing constraint OFFSET IN(the second covers 0 paths):

 

Timing constraint: OFFSET = IN 1 ns VALID 2 ns BEFORE COMP "dco_p" "RISING";

 4 paths analyzed, 4 endpoints analyzed, 4 failing endpoints
 4 timing errors detected. (4 setup errors, 0 hold errors)
 Minimum allowable offset is   3.644ns.
--------------------------------------------------------------------------------
Slack:                  -2.644ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               ch_p (PAD)
  Destination:          iddr_inst/iddr_inst/IDDR2.C0Q0/FF0 (FF)
  Destination Clock:    IntRxClk rising at 0.000ns
  Requirement:          1.000ns
  Data Path Delay:      5.867ns (Levels of Logic = 0)
  Clock Path Delay:     2.223ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ch_p to iddr_inst/iddr_inst/IDDR2.C0Q0/FF0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A12.ICLK1            Tiopickd              5.867   ch_p
                                                       ch_p
                                                       ibuf_inst/IBUFDS
                                                       ch_p.DELAY_ADJ
                                                       iddr_inst/iddr_inst/IDDR2.C0Q0/FF0
    -------------------------------------------------  ---------------------------
    Total                                      5.867ns (5.867ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: dco_p to iddr_inst/iddr_inst/IDDR2.C0Q0/FF0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A9.I                 Tiopi                 0.419   dco_p
                                                       dco_p
                                                       CLKIN_IBUFGDS_INST/IBUFDS
                                                       dco_p.DELAY_ADJ
    DCM_X2Y3.CLKIN       net (fanout=1)        2.421   ClkToDCM
    DCM_X2Y3.CLK0        Tdmcko_CLK           -2.528   DCM_SP_INST
                                                       DCM_SP_INST
    BUFGMUX_X1Y11.I0     net (fanout=1)        0.302   ClkDCMtoBUF0
    BUFGMUX_X1Y11.O      Tgi0o                 0.199   CLK0_BUFG_INST
                                                       CLK0_BUFG_INST
    A12.ICLK1            net (fanout=3)        1.410   IntRxClk
    -------------------------------------------------  ---------------------------
    Total                                      2.223ns (-1.910ns logic, 4.133ns route)

...
--------------------------------------------------------------------------------
Slack:                  -0.645ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               ch_p (PAD)
  Destination:          iddr_inst/iddr_inst/IDDR2.C0Q0/FF1 (FF)
  Destination Clock:    IntRxClkNot rising at 2.000ns
  Requirement:          1.000ns
  Data Path Delay:      5.867ns (Levels of Logic = 0)
  Clock Path Delay:     2.222ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: ch_p to iddr_inst/iddr_inst/IDDR2.C0Q0/FF1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A12.ICLK2            Tiopickd              5.867   ch_p
                                                       ch_p
                                                       ibuf_inst/IBUFDS
                                                       ch_p.DELAY_ADJ
                                                       iddr_inst/iddr_inst/IDDR2.C0Q0/FF1
    -------------------------------------------------  ---------------------------
    Total                                      5.867ns (5.867ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: dco_p to iddr_inst/iddr_inst/IDDR2.C0Q0/FF1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A9.I                 Tiopi                 0.419   dco_p
                                                       dco_p
                                                       CLKIN_IBUFGDS_INST/IBUFDS
                                                       dco_p.DELAY_ADJ
    DCM_X2Y3.CLKIN       net (fanout=1)        2.421   ClkToDCM
    DCM_X2Y3.CLK180      Tdmcko_CLK           -2.528   DCM_SP_INST
                                                       DCM_SP_INST
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.312   ClkDCMtoBUF180
    BUFGMUX_X2Y11.O      Tgi0o                 0.199   CLK180_BUFG_INST
                                                       CLK180_BUFG_INST
    A12.ICLK2            net (fanout=1)        1.399   IntRxClkNot
    -------------------------------------------------  ---------------------------
    Total                                      2.222ns (-1.910ns logic, 4.132ns route)

--------------------------------------------------------------------------------
 

I have tried to lower the Fmax, but with 125 MHz it is still impossible to meet timing.

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ywu
Xilinx Employee
Xilinx Employee
12,386 Views
Registered: ‎11-28-2007

A couple of things:

 

1. For your constraint "TIMESPEC TS_dco_p = PERIOD "dco_p" 250 MHz HIGH 50%;", the string after PERIOD is a timing group name that needs to be defined first. e.g

    NET dco_p TNM_NET = dco_p;

 

 2.You use CLK0 and CLK180 to drive IDDR. In the tool points of view. the RISING edges of CLK0 and CLK180 are used for capturing data. The rising edges are then referenced back to the rising edge of dco_p. This is why the constraint on the failling edge of dco_p is ignored. Instead, you will see the offset in constraint on the falling edge of dco_p show up on the rising edge but the clock is referenced to CLK180. If you want to see the tool to take both rising edge and falling edge offset in constraints of dco_p, you can replace the CLK180 with an inverted clock of CLK0. e.g. 

replace

CLK180_BUFG_INST : BUFG port map (I=>ClkDCMtoBUF180,O=>IntRxClkNot);

with

IntRxClkNot <= not IntRxClk;

 

Cheers,

Jim

 

 

 

Cheers,
Jim
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ivan.mironenko
Contributor
Contributor
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Registered: ‎09-10-2008

Hi,

 

thank you for detailed explanation of how the constraints propogate through the DCM.

This is actually the first time I see it in such detail. In all pdfs I read it is just "magically propogates through everything", and then everything should be fine:)

Ok, this means that I do not need the second constraint (OFFSET = IN 2 ns BEFORE dco_n FALLING;) and  I also do not need RISING modifier for the first OFFSET constraint.
By the way, I had a TNM_NET constraint in my ucf.

 

Now my ucf file looks as follows:

 

NET "dco_n" TNM_NET = dco_n;
TIMESPEC TS_dco_n = PERIOD "dco_n" 125 MHz HIGH 50%;
OFFSET = IN 2 ns BEFORE dco_n;

 

 

But the design still does not meet timing.

From the timing report, i can see that the data path is very long(5.867ns), and for some reason includes DELAY_ADJ delay.

 

Moreover, as I understand, the DCM working in SOURCE_SYNCRONOUS mode should deskew the clock in such a way, that the   Pad-to-Clock relationship at the IDD2 have exactly the same Pad-to-Clock relationship as they had at the package pins, but it is not true in my case:

 Minimum Clock Path: dco_n to iddr_inst/iddr_inst/IDDR2.C0Q0/FF0 2.223ns

 

I have also  got an advice to shift the phase of the clock by 1.5ns(why 1.5ns???) using   CLKOUT_PHASE_SHIFT => "FIXED" and PHASE_SHIFT => 65 parameters for DCM,

 and apparently it works. I mean, the timing analyzer says that the constraints were met, but I still have some doubts.

Why should the fixed phase shift be introduced, if the only thing which is required is to instantiate appropriate delay buffers in DCM and IBUF?

 

Should not it be all automatic?

Message Edited by ivan.mironenko on 19-02-2009 07:56 PM
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prdorrell
Adventurer
Adventurer
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Registered: ‎03-05-2008

Hello all,

 

I have a very similar problem to Ivan so I'm appending mine to this thread ....

 

The problem is specifying a setup constraint for the data latched in the IDDR2 on the *negative* edge of the bit clock:

Like Ivan I'm using a Spartan-3A-DSP. I want to deserialise the serial output of an ADC. I take the DDR bit clock of 280MHz, put it through a DCM:

 

 

    DCM_SP_INST : DCM_SP
   generic map( CLK_FEEDBACK => "2X",
            CLKDV_DIVIDE => 3.5,
            CLKFX_DIVIDE => 1,
            CLKFX_MULTIPLY => 2,
            CLKIN_DIVIDE_BY_2 => TRUE,
            CLKIN_PERIOD => 7.143,
            CLKOUT_PHASE_SHIFT => "FIXED",
            DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
            DFS_FREQUENCY_MODE => "LOW",
            DLL_FREQUENCY_MODE => "LOW",
            DUTY_CYCLE_CORRECTION => TRUE,
            FACTORY_JF => x"C080",
            PHASE_SHIFT => 31,
            STARTUP_WAIT => FALSE)
      port map (CLKFB=>CLKFB_IN,
                CLKIN=>CLKIN_IN,
                DSSEN=>GND_BIT,
                PSCLK=>GND_BIT,
                PSEN=>GND_BIT,
                PSINCDEC=>GND_BIT,
                RST=>RST_IN,
                CLKDV=>CLKDV_BUF,
                CLKFX=>open,
                CLKFX180=>open,
                CLK0=>open,
                CLK2X=>CLK2X_BUF,
                CLK2X180=>CLK2X180_BUF,
                CLK90=>open,
                CLK180=>open,
                CLK270=>open,
                LOCKED=>LOCKED_OUT,
                PSDONE=>open,
                STATUS=>open);

Since my Spartan 3A-DSP is -4 speed grade, the DCM cannot take 280MHz so I've selected CLKIN_DIVIDE_BY_2 => TRUE, and take buffered CLK2X and CLK2X180 to clock the IDDR2 for the ADC data. Here are my constraints:

 

NET "AdcBitClk_p" TNM_NET = "AdcBitClk_p";

TIMESPEC "TS_AdcBitClk_p" = PERIOD "AdcBitClk_p" 280 MHz HIGH 50%;

 

##Notice both the pins below are the positive half of LVDS pairs.
INST "AdcData_p<0>" TNM = AdcDataFrame_GROUP; ##This is the first data channel of the ADC
INST "AdcFrame_p"   TNM = AdcDataFrame_GROUP;  ##This is the frame clock at 40MHz from the ADC (i.e. at sample rate)

 

##This is the offset constraint ... i.e. the AdcBitClk_p occurs midway through the data eye.
TIMEGRP "AdcDataFrame_GROUP" OFFSET = IN 893 ps BEFORE "AdcBitClk_p";

 

Here is a bit of my timing report:

 

================================================================================
Timing constraint: TIMEGRP "AdcDataFrame_GROUP" OFFSET = IN 0.893 ns BEFORE
COMP "AdcBitClk_p";

 3 paths analyzed, 3 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   0.891ns.
--------------------------------------------------------------------------------
Slack:                  0.002ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               AdcData_p<0> (PAD)
  Destination:          Gen2[0].Inst_AdcData_IDDR2/Gen2[0].Inst_AdcData_IDDR2/IDDR2.C0Q0/FF0 (FF)
  Destination Clock:    AdcBitClock rising at 0.432ns
  Requirement:          0.893ns
  Data Path Delay:      2.589ns (Levels of Logic = 0)
  Clock Path Delay:     1.266ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: AdcData_p<0> to Gen2[0].Inst_AdcData_IDDR2/Gen2[0].Inst_AdcData_IDDR2/IDDR2.C0Q0/FF0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B23.ICLK1            Tiopick               2.589   AdcData_p<0>
                                                       AdcData_p<0>
                                                       Gen1[0].Inst_AdcData_IBUFDS/IBUFDS
                                                       AdcData_p<0>.DELAY_ADJ
                                                       Gen2[0].Inst_AdcData_IDDR2/Gen2[0].Inst_AdcData_IDDR2/IDDR2.C0Q0/FF0
    -------------------------------------------------  ---------------------------
    Total                                      2.589ns (2.589ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: AdcBitClk_p to Gen2[0].Inst_AdcData_IDDR2/Gen2[0].Inst_AdcData_IDDR2/IDDR2.C0Q0/FF0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B13.I                Tiopi                 1.203   AdcBitClk_p
                                                       AdcBitClk_p
                                                       Inst_AdcClock_IBUFGDS/IBUFDS
                                                       AdcBitClk_p.DELAY_ADJ
    DCM_X1Y3.CLKIN       net (fanout=1)        0.729   AdcBitClkIn
    DCM_X1Y3.CLK2X       Tdmcko_CLK2X         -2.515   Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/DCM_SP_INST
                                                       Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/DCM_SP_INST
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.293   Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/CLK2X_BUF
    BUFGMUX_X2Y11.O      Tgi0o                 0.199   Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/CLK2X_BUFG_INST
                                                       Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/CLK2X_BUFG_INST
    B23.ICLK1            net (fanout=24)       1.357   AdcBitClock
    ------------------------------------------------  ---------------------------
    Total                                      1.266ns (-1.113ns logic, 2.379ns route)

You'll see I've adjusted the clock phase through the DCM to achieve positive slack on the above setup requirement. Now looking at the negative clocked side:

 

--------------------------------------------------------------------------------
Slack:                  1.708ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               AdcData_p<0> (PAD)
  Destination:          Gen2[0].Inst_AdcData_IDDR2/Gen2[0].Inst_AdcData_IDDR2/IDDR2.C0Q0/FF1 (FF)
  Destination Clock:    AdcBitClock180 rising at 2.218ns
  Requirement:          0.893ns
  Data Path Delay:      2.589ns (Levels of Logic = 0)
  Clock Path Delay:     1.186ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: AdcData_p<0> to Gen2[0].Inst_AdcData_IDDR2/Gen2[0].Inst_AdcData_IDDR2/IDDR2.C0Q0/FF1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B23.ICLK2            Tiopick               2.589   AdcData_p<0>
                                                       AdcData_p<0>
                                                       Gen1[0].Inst_AdcData_IBUFDS/IBUFDS
                                                       AdcData_p<0>.DELAY_ADJ
                                                       Gen2[0].Inst_AdcData_IDDR2/Gen2[0].Inst_AdcData_IDDR2/IDDR2.C0Q0/FF1
    -------------------------------------------------  ---------------------------
    Total                                      2.589ns (2.589ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: AdcBitClk_p to Gen2[0].Inst_AdcData_IDDR2/Gen2[0].Inst_AdcData_IDDR2/IDDR2.C0Q0/FF1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B13.I                Tiopi                 1.203   AdcBitClk_p
                                                       AdcBitClk_p
                                                       Inst_AdcClock_IBUFGDS/IBUFDS
                                                       AdcBitClk_p.DELAY_ADJ
    DCM_X1Y3.CLKIN       net (fanout=1)        0.729   AdcBitClkIn
    DCM_X1Y3.CLK2X180    Tdmcko_CLK2X         -2.515   Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/DCM_SP_INST
                                                       Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/DCM_SP_INST
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.257   Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/CLK2X180_BUF
    BUFGMUX_X2Y10.O      Tgi0o                 0.199   Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/CLK2X180_BUFG_INST
                                                       Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/CLK2X180_BUFG_INST
    B23.ICLK2            net (fanout=1)        1.313   AdcBitClock180
    -------------------------------------------------  ---------------------------
    Total                                      1.186ns (-1.113ns logic, 2.299ns route)

... but of course this passes because the timing analyser has allowed itself another half a bit clock period! i.e. the same setup as for the positive going clocked data. This is surely not right! Furthemore, if I add a VALID time into the OFFSET constraint ....

 

TIMEGRP "AdcDataFrame_GROUP" OFFSET = IN 893 ps VALID 1786 ps BEFORE "AdcBitClk_p";

... then the timing analyser complains about hold violations on the negative clocked data:

 

 --------------------------------------------------------------------------------

Hold Paths: TIMEGRP "AdcDataFrame_GROUP" OFFSET = IN 0.893 ns VALID 1.786 ns BEFORE COMP
        "AdcBitClk_p";
--------------------------------------------------------------------------------
Slack (hold path):      -1.669ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               AdcData_p<0> (PAD)
  Destination:          Gen2[0].Inst_AdcData_IDDR2/Gen2[0].Inst_AdcData_IDDR2/IDDR2.C0Q0/FF1 (FF)
  Destination Clock:    AdcBitClock180 rising at 2.218ns
  Requirement:          0.893ns
  Data Path Delay:      1.307ns (Levels of Logic = 0)
  Clock Path Delay:     1.651ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Minimum Data Path: AdcData_p<0> to Gen2[0].Inst_AdcData_IDDR2/Gen2[0].Inst_AdcData_IDDR2/IDDR2.C0Q0/FF1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B23.ICLK2            Tioickp     (-Th)    -1.307   AdcData_p<0>
                                                       AdcData_p<0>
                                                       Gen1[0].Inst_AdcData_IBUFDS/IBUFDS
                                                       AdcData_p<0>.DELAY_ADJ
                                                       Gen2[0].Inst_AdcData_IDDR2/Gen2[0].Inst_AdcData_IDDR2/IDDR2.C0Q0/FF1
    -------------------------------------------------  ---------------------------
    Total                                      1.307ns (1.307ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Maximum Clock Path: AdcBitClk_p to Gen2[0].Inst_AdcData_IDDR2/Gen2[0].Inst_AdcData_IDDR2/IDDR2.C0Q0/FF1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B13.I                Tiopi                 1.308   AdcBitClk_p
                                                       AdcBitClk_p
                                                       Inst_AdcClock_IBUFGDS/IBUFDS
                                                       AdcBitClk_p.DELAY_ADJ
    DCM_X1Y3.CLKIN       net (fanout=1)        0.911   AdcBitClkIn
    DCM_X1Y3.CLK2X180    Tdmcko_CLK2X         -2.654   Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/DCM_SP_INST
                                                       Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/DCM_SP_INST
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.321   Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/CLK2X180_BUF
    BUFGMUX_X2Y10.O      Tgi0o                 0.221   Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/CLK2X180_BUFG_INST
                                                       Inst_AdcDeserialiserDcmWrapper/Inst_AdcDeserialiserDcm/CLK2X180_BUFG_INST
    B23.ICLK2            net (fanout=1)        1.544   AdcBitClock180
    -------------------------------------------------  ---------------------------
    Total                                      1.651ns (-1.125ns logic, 2.776ns route)

 

So, in summary, please can someone tell me how to setup constraints to handle the negative clocked data setup time into a IDDR2.

 

Kind regards

Paul Dorrell 

 

 

 

 

 

clocks to    which . have an ADC with an output DDR bit clock of 280MHz  to deserialise an input from an ADC.

 

 

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ivan.mironenko
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Registered: ‎09-10-2008

Hi Paul,

 

After quite a lot of struggling with this problem, I came to the conclusion that the easiest way is to abandon this approach, and use the Dynamic Phase Adjustment(or whatever it is called).

You wwill spend much less time writing and debugging the state machine for that, then you would spend trying to figure out how to apply DDR constraints.

 

There are a couple of whitepapers at xilinx.com about that, and if you have any further problems, you can ask here.

 

 

P.S. I opened a webcase exactly for this issue, wrote countless numbers of emails trying to explain the problem(of course, you know how it works:

http://forums.xilinx.com/xlnx/board/message?board.id=ForumU&message.id=30&query.id=723529#M31 ),

it lasted for almost a month, and then I closed the webcase because it was easier and faster to implement the dynamic phase adjustment then to explain 100th time what I really want to achieve..

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prdorrell
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Registered: ‎03-05-2008

Thanks Ivan,

 

after reading about your troubles trying to get a sensible response to your web case ... I think I'll give up on IDDR2 offset constraints and try the Dynamic Phase Adjustment approach.

 

Cheers

Paul

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xlsman
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Can you give me the XAPP866? E-mail:xuls@ihep.ac.cn.Thank you!

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endab
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nola94
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Registered: ‎11-04-2009

Hi Ivan,

 

I am trying to combine texas Instruments ADS5282EVM ADC with Spartan 3a DSP 3400 Development platform.

 

I have done this before using a SPartan 6 device.

 

however with spartan 3a dsp 3400 i am facing some problems.

 

I am using a DCM to provide the DDR cells with the data capture clock (and its mirror) provided by ADS5282.

 

When using Cipscope these clocks seems to have much different frequency from the expected.

 

Could you send me your code for proper capturing ADC data inside Spartan 3ADSP 3400 FPGA?

 

regards,

 

Lefteris

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ivan.mironenko
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Registered: ‎09-10-2008

nola94,

Are you sure it is a good idea to capture ADC clock with Chipscope?

Maybe it is a better idea to configure your ADC chip to generate some training sequence and capture that sequence on the ouput of your IDDR2 primitives?

 

 

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nola94
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Registered: ‎11-04-2009

Hi Ivan,

 

thanks for the prompt reply!

 

I use test patterns but i got corrupted results. Something is happening with the capture clocks. Thats why i use Chipscope.

 

 I changed the trigger clock in Chipscope(much higher frequency than the data capture clock and frame clock of the ADC) and now results are reasonable. However, data are in phase with the data capture clock even if ADC is programmed to have some phase(in the middle of the data eye). When tried to use another configuration from ADC same thing happen. Also i have the same results when i use a fixed phase shift value in the DCM.

 

Can you tell me why you propose to not use Chipscope?

What are my alternatives when i want to watch the clocks along with data..?

 

When i simulate the design everything goes fine....

 

Regards,

 

Lefteris

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rcingham
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"When i simulate the design everything goes fine...."

Simulations (unless post-PAR) do not have delay timings. As various other threads note, high-speed source-synchronous data capture is not trivial.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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nola94
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Registered: ‎11-04-2009

Should it Chipscope show timing Delays? This is the main question...

 

Do you have any suggestions about monitoring my signals and see what goes wrong?

 

I agree that it is not trivial, thats why i am writing to the forum....

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mcgett
Xilinx Employee
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Registered: ‎01-03-2008

> Should it Chipscope show timing Delays?

 

I'm slightly unsure what you mean by "show timing delays".

 

ChipScope display the values that the ILA core captured using the rising edge of the clock that was provided. 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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nola94
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Can i see in Chipscope the delays in signals produce for example by the use of a buffer?

 

While in the simulation everything seem to work fine; in real hardware there are some delays in clocks and data lines that have as a result data not captured in the middle of the clock eye which results in capture corrupted data....

 

 

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mcgett
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Registered: ‎01-03-2008

> Can i see in Chipscope the delays in signals produce for example by the use of a buffer?

 

You will see the result of any delays to the register that the ILA used to capture the data.  This will not be the same delay as seen by any other register in the design.

 

You need to be using IDDR2 input registers in your design. 

You need to analyze the timing against your ADC datasheet.

You need to apply proper timing constraints to these inputs in your design.

And you need to simulate with the back-annotated timing constraints with a test bench that properly emulates the min/max conditions of the ADC datasheet.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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