UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor hayesk
Visitor
231 Views
Registered: ‎02-19-2019

Artix-7 axi_quad_spi_0 set_multicycle_path "No object(s) found for -to" error. (Vivado 2016.4)

  Hello,

  Thank you in advance for reviewing my issue.  I have a simple MicroBlaze core connected to a single AXI Quad SPI interface with STARTUP Disabled, and I'm having difficulty with the 'set_multicycle_path' directive as defined in the SPI interface documentation.  I am getting a "No valid object(s) found" error as shown below.  My Block Design ('clk_out1' is connected to 'ext_spi_clk') details and constraints are as follows:

ClkWiz.PNG

 

AxiQSpi.PNG

 

Signals.PNG

 

Constraints up to point of error (directive #12):

set tco_max 7
set tco_min 1
set tsu 2
set th 3
set tdata_trace_delay_max 0.25
set tdata_trace_delay_min 0.25
set tclk_trace_delay_max 0.2
set tclk_trace_delay_min 0.2
create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_0/ext_spi_clk] -edges {3 5 7} [get_ports spi*_sck_io]
set_input_delay -clock clk_sck -max [expr $tco_max + $tdata_trace_delay_max + $tclk_trace_delay_max] [get_ports spi_0_io*_io] -clock_fall;
set_input_delay -clock clk_sck -min [expr $tco_min + $tdata_trace_delay_min + $tclk_trace_delay_min] [get_ports spi_0_io*_io] -clock_fall;

# PROBLEM: "-to [get_clocks..." section fails to locate clocks.
set_multicycle_path 2 -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]

 

The error is as follows:

[Vivado 12-4739] set_multicycle_path:No valid object(s) found for '-to [get_clocks -of_objects [get_pins [list eSR19_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/ext_spi_clk eSR19_i/axi_quad_spi_0/U0/ext_spi_clk eSR19_i/axi_quad_spi_0/ext_spi_clk]]]'. ["D:/DdcMicroBlazeWithSpi/eSR19.srcs/constrs_1/new/constraints.xdc":14]

 

  I have searched the forums to no avail.  If further details are required, I will provide them promptly.

    Thank You.  Any insights greatly appreciated.

        Keith

 

 

0 Kudos
7 Replies
Moderator
Moderator
192 Views
Registered: ‎11-04-2010

Re: Artix-7 axi_quad_spi_0 set_multicycle_path "No object(s) found for -to" error. (Vivado 2016.4)

Hi, @hayesk ,

1. Please check whether the set_multicycle_path works in the synthesized deisgn.

   <1> Open the synthesized design

   <2> report_timing -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -name test

2. Please confirm that the set_multicycle_path constraint is executed after the create_clock constriant.

You can try to print the compile order of the xdc files with the below command:

report_compile_order -constraints

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Visitor hayesk
Visitor
181 Views
Registered: ‎02-19-2019

Re: Artix-7 axi_quad_spi_0 set_multicycle_path "No object(s) found for -to" error. (Vivado 2016.4)

Thank you for the quick response.

For item 1 (Synthesis), it seems that I get a similar error message:

report_timing -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -name test
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]'.
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks.
INFO: [Vivado 12-2286] Implicit search of objects for pattern 'clk_sck' matched to 'clock' objects.
Resolution: To avoid ambiguous patterns, provide proper objects using get commands e.g. [get_nets xyz].
ERROR: [Vivado 12-4739] report_timing:No valid object(s) found for '-to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]'.
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.

 

The compile order is as follows (Sorry for all of the text):

Constraint evaluation order for 'synthesis' with fileset 'sources_1' & with fileset 'constrs_1':
Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name
----- ---------------------------------- ------------ ------------------------ --------------- ---------------- -------------- --------------------------------------------------------------------------------------------------------------------
1 eSR19_proc_sys_reset_0_0_board.xdc Synth & Impl eSR19_proc_sys_reset_0_0 U0 EARLY d:/DdcMicroBlazeWithSpi/eSR19.srcs/sources_1/bd/eSR19/ip/eSR19_proc_sys_reset_0_0/eSR19_proc_sys_reset_0_0_board.xdc
2 eSR19_proc_sys_reset_0_0.xdc Synth & Impl eSR19_proc_sys_reset_0_0 U0 EARLY d:/DdcMicroBlazeWithSpi/eSR19.srcs/sources_1/bd/eSR19/ip/eSR19_proc_sys_reset_0_0/eSR19_proc_sys_reset_0_0.xdc
3 eSR19_microblaze_0_0.xdc Synth & Impl eSR19_microblaze_0_0 U0 EARLY d:/DdcMicroBlazeWithSpi/eSR19.srcs/sources_1/bd/eSR19/ip/eSR19_microblaze_0_0/eSR19_microblaze_0_0.xdc
4 eSR19_lmb_v10_0_0.xdc Synth & Impl eSR19_lmb_v10_0_0 U0 EARLY d:/DdcMicroBlazeWithSpi/eSR19.srcs/sources_1/bd/eSR19/ip/eSR19_lmb_v10_0_0/eSR19_lmb_v10_0_0.xdc
5 eSR19_lmb_v10_1_0.xdc Synth & Impl eSR19_lmb_v10_1_0 U0 EARLY d:/DdcMicroBlazeWithSpi/eSR19.srcs/sources_1/bd/eSR19/ip/eSR19_lmb_v10_1_0/eSR19_lmb_v10_1_0.xdc
6 eSR19_util_ds_buf_0_0_board.xdc Synth & Impl eSR19_util_ds_buf_0_0 U0 EARLY d:/DdcMicroBlazeWithSpi/eSR19.srcs/sources_1/bd/eSR19/ip/eSR19_util_ds_buf_0_0/eSR19_util_ds_buf_0_0_board.xdc
7 eSR19_clk_wiz_0_1_board.xdc Synth & Impl eSR19_clk_wiz_0_1 inst EARLY d:/DdcMicroBlazeWithSpi/eSR19.srcs/sources_1/bd/eSR19/ip/eSR19_clk_wiz_0_1/eSR19_clk_wiz_0_1_board.xdc
8 eSR19_clk_wiz_0_1.xdc Synth & Impl eSR19_clk_wiz_0_1 inst EARLY d:/DdcMicroBlazeWithSpi/eSR19.srcs/sources_1/bd/eSR19/ip/eSR19_clk_wiz_0_1/eSR19_clk_wiz_0_1.xdc
9 eSR19_axi_quad_spi_0_0_board.xdc Synth & Impl eSR19_axi_quad_spi_0_0 U0 EARLY d:/DdcMicroBlazeWithSpi/eSR19.srcs/sources_1/bd/eSR19/ip/eSR19_axi_quad_spi_0_0/eSR19_axi_quad_spi_0_0_board.xdc
10 eSR19_axi_quad_spi_0_0.xdc Synth & Impl eSR19_axi_quad_spi_0_0 U0 EARLY d:/DdcMicroBlazeWithSpi/eSR19.srcs/sources_1/bd/eSR19/ip/eSR19_axi_quad_spi_0_0/eSR19_axi_quad_spi_0_0.xdc
11 constraints.xdc Synth & Impl NORMAL D:/DdcMicroBlazeWithSpi/eSR19.srcs/constrs_1/new/constraints.xdc
12 eSR19_axi_quad_spi_0_0_clocks.xdc Synth & Impl eSR19_axi_quad_spi_0_0 U0 LATE d:/DdcMicroBlazeWithSpi/eSR19.srcs/sources_1/bd/eSR19/ip/eSR19_axi_quad_spi_0_0/eSR19_axi_quad_spi_0_0_clocks.xdc

 

I just noticed index 12 of the report is related to the QSpi clocks, and it's late in the processing order.  Should my 'constraints.xdc' be the last to get processed?

 

0 Kudos
Moderator
Moderator
168 Views
Registered: ‎11-04-2010

Re: Artix-7 axi_quad_spi_0 set_multicycle_path "No object(s) found for -to" error. (Vivado 2016.4)

It looks the create_clock command for ext_spi_clk pin doesn't take effect.

Which XDC file contains the create_clock command?

Please check whether the target clock is created with properly with report_clocks command.

 

Please also try to modify the command to search the pin in your command:

get_pins -hierarchical */ext_spi_clk  => 

get_pin -hier -filter {NAME =~ */ext_spi_clk}

In your synthesized design, you can check whether the pin is searched correctly:

select_object [get_pin -hier -filter {NAME =~ */ext_spi_clk}]

 

 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Visitor hayesk
Visitor
161 Views
Registered: ‎02-19-2019

Re: Artix-7 axi_quad_spi_0 set_multicycle_path "No object(s) found for -to" error. (Vivado 2016.4)

  Again, thank you for your prompt attention on this issue.

The 'report_clocks' command offered the following:

Clock Report

Attributes
P: Propagated
G: Generated
V: Virtual
I: Inverted

Clock      Period(ns)   Waveform(ns)   Attributes   Sources
clk_sck   0.000           {}                       P,G             {spi_0_sck_io}

====================================================
Generated Clocks
====================================================

Generated Clock : clk_sck
Master Source : eSR19_i/axi_quad_spi_0/ext_spi_clk
Edges : {3 5 7}
Generated Sources : {spi_0_sck_io}

 

Both 'get_pins' commands display the following:

eSR19_i/axi_quad_spi_0/ext_spi_clk eSR19_i/axi_quad_spi_0/U0/ext_spi_clk eSR19_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/ext_spi_clk

 

The 'select_objects' command displayed the following:

INFO: [Coretcl 2-6] '3' objects selected.

 

0 Kudos
Moderator
Moderator
149 Views
Registered: ‎11-04-2010

Re: Artix-7 axi_quad_spi_0 set_multicycle_path "No object(s) found for -to" error. (Vivado 2016.4)

Hi, @hayesk ,

There is only one clock, which is generated clock in the design.

Please don't forget to create the master clock of the generated clock clk_sck .

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Visitor hayesk
Visitor
133 Views
Registered: ‎02-19-2019

Re: Artix-7 axi_quad_spi_0 set_multicycle_path "No object(s) found for -to" error. (Vivado 2016.4)

Do I need to create a master clock manually?  I figured the 'clk_wiz_0' block took care of that.  The 'clk_wiz_0_clk_out1' net is connected directly to the 'ext_spi_clk' input.  Do I need to associate or link them in some fashion?

0 Kudos
Moderator
Moderator
124 Views
Registered: ‎11-04-2010

Re: Artix-7 axi_quad_spi_0 set_multicycle_path "No object(s) found for -to" error. (Vivado 2016.4)

Hi, @hayesk ,

Yes, You need create a create_clock constraint for in your XDC manually on the port (As input of clk_wiz_0), then the output clock of clk_wiz_0 will be derived automatically.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos