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Explorer
Explorer
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Registered: ‎05-16-2014

Assigning a constraint to an Entity

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I would like to assign a constraint to an entity.

However, when you search for the Start Point, or End Points the entity name does not appear by itself. Only signals associated with that entity.

How do you get the entire entity?

For example currently I have the following:

set_false_path -from [get_pins UClkGen/Clk120MRstXI_reg/C] .

Don't want this. Want to have:

set_false_path -from [get_pins UClkGen/Clk120MRstXI_reg/C]  -to ENTITY_NAME

What is the syntax for the ENTITY_NAME?

 

Thanks.

 

 

 

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Guide
Guide
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Registered: ‎01-23-2009

What do you mean by ENTITY_NAME?

An entity in VHDL is the definition of some digital structure - the definition of some functionality.

The entity doesn't actually exist in your design - only instances of that entity do; you can instantiate one or more instances of that entity.

Assuming you mean a specific instance of that entity, what are you really trying to do?

A static timing path starts at a static timing starpoint; a clock pin of a clocked primitive cell, the cell itself, an input port or a clock;  yours is the clock pin of a (presumably clocked primitive) cell. A static timing path ends at a static timing endpoint; a data pin of a clocked primitive cell, the cell itself, an output port or a clock; - an instance of an entity is none of these. In Vivado, you can only constrain static timing paths.

So are you trying to constrain all paths that start at this start point and "end at any valid endpoint within the hierarchy of this instance of the cell"?

If so, the command would be something like

set_false_path -from [get_pins UClkGen/Clk120MRstXI_reg/C] -to [get_cells -hier -filter {(NAME =~ <full_hierarchical_path_name_to_instance>/*) && IS_PRIMITIVE && IS_SEQUENTIAL}]

(Of course, I should probably ask the follow on question - are you sure these paths are false? Reset paths are rarely false...)

Avrum

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @swimteam ,

If your requirement is to apply set_false_path on entity, i guess you need to use get_cells instead of get_pins.

Thanks,

Raj

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Guide
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Registered: ‎01-23-2009

What do you mean by ENTITY_NAME?

An entity in VHDL is the definition of some digital structure - the definition of some functionality.

The entity doesn't actually exist in your design - only instances of that entity do; you can instantiate one or more instances of that entity.

Assuming you mean a specific instance of that entity, what are you really trying to do?

A static timing path starts at a static timing starpoint; a clock pin of a clocked primitive cell, the cell itself, an input port or a clock;  yours is the clock pin of a (presumably clocked primitive) cell. A static timing path ends at a static timing endpoint; a data pin of a clocked primitive cell, the cell itself, an output port or a clock; - an instance of an entity is none of these. In Vivado, you can only constrain static timing paths.

So are you trying to constrain all paths that start at this start point and "end at any valid endpoint within the hierarchy of this instance of the cell"?

If so, the command would be something like

set_false_path -from [get_pins UClkGen/Clk120MRstXI_reg/C] -to [get_cells -hier -filter {(NAME =~ <full_hierarchical_path_name_to_instance>/*) && IS_PRIMITIVE && IS_SEQUENTIAL}]

(Of course, I should probably ask the follow on question - are you sure these paths are false? Reset paths are rarely false...)

Avrum

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Registered: ‎05-16-2014

The constraints were already in Altera which had a false path for the entity. I'm  porting to Xilinx.

I found that using cells the entity name showed up. So, now I have:

set_false_path -from [get_pins UClkGen/Clk120MRstXI_reg/C] -to [get_cells UDigitalTuner0/*]

I had to add the "/*" since the no valid endpoint error poped up. But now Vivado accepts the above syntax.

 

Should I use your syntax instead?

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Guide
Guide
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Registered: ‎01-23-2009

Should I use your syntax instead?

Yes, there are several potential problems with your syntax:

  • If there are any sub-modules of this instance (i.e. there are other entities instantiated in this instance) then your command will not apply to the clocked cells within the sub-modules
  • (Less importantly) your command is less efficient, the "-to" you are specifying will include sequential cells as well as combinatorial cells and hierarchical cells. While harmless, this will be a bit slower

Avrum

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Explorer
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Registered: ‎05-16-2014

How do you find the "full hierarchicial path?"

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Registered: ‎01-23-2009

How do you find the "full hierarchicial path?"

My guess is it's just "UDigitalTuner0" - it looks like UDigitalTuner0 is an instance in the top level of the design, and hence this is the full hierarchical path.
 
If the instance was deeper inside the hierarchy - for example the top level instantiates instance A, which instantiates instance B which instantiates instance C and you wanted to disable paths to UDigitalTuner0 which was instantiated within that, then the full hierarchical path would have been "A/B/C/UDigitalTuner0" 
 
Avrum
 
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Registered: ‎05-16-2014

You're right. The command is now:

set_false_path -from [get_pins UClkGen/Clk120MRstXI_reg/C] -to [get_cells -hier -filter {(NAME =~ UDigitalTuner0/*) && IS_PRIMITIVE && IS_SEQUENTIAL}]

This works.

So you only want the "instance name" and not the entity name. This syntax will then make the reset a false path to not only th Digital Tuner but also any instances that are in it. Is that right?

 

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Registered: ‎01-23-2009

This syntax will then make the reset a false path to not only th Digital Tuner but also any instances that are in it. Is that right?

Yes.

But I repeat my earlier statement - Reset paths are rarely able to be treated as false paths. If you declare reset as a false path without the necessary mechanisms to ensure that it really is then your design will fail to reliably come out of reset.

Regardless of whether you are using synchronous set/reset pins of your flip-flops or "asynchronous" preset/clear pins of your flip-flop, the reset signal to those pins must be synchronous - for the preset/clear only the deasserting edge must be synchronous, but it must be synchronous.

The only way a reset can be declared as a false path is if you ensure that the design is completely stable around the deasserting edge of reset - this either means gating your clock around the deasserting edge of reset, or having some other synchronous condition that holds the design in a "reset-like" condition around the deasserting edge of reset. 

To be very clear - just because you are using "asynchronous preset/clear" on your flip-flops is not a sufficient reason to declare the reset as a false path.

Avrum

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Registered: ‎05-16-2014

Thanks Avrum. I will bring this up at the next meeting.

 

Swimteam

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