UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
13,227 Views
Registered: ‎09-10-2008

Asynchronous FIFO multicycle timing constraints. Is it actually possible?

Jump to solution

Hi,

I have a design where I have to stream the data from the external LVDS ADC to the DDR.
The LVDS receiver/deserializer uses the clock provided by ADC(280MHz), and the rest of the system uses the onboard 125MHz clock generator

(I use Spartan3A-DSP 1800 development board).

Since the ADC and the system clocks are asynchronous, I have connected the ADC deserializer to the rest of the system through the asynchronous FIFO generated by Coregen.
The wr_clk of the FIFO is connected to the ADC clock, and the wr_en is connected to the 'valid' signal available from the deserializer.
The 'valid' signal has frequency of 40MHz.

 

Now the problem. The design can  not meet timing in this fifo because of the fast ADC clock.
I have  tried to create a multicycle constraint for the write side of the fifo based on the 'valid' signal:

 

TIMESPEC TS_Ads_00 = PERIOD IntRxClk  280 Mhz;                                                                                       # ADC clock for 14bitx40 MHz
NET "*adc_dma_plb_0/USER_LOGIC_I/adc_int_inst/RX_box*valid*"  TNM_NET = VALID_TNM;
TIMESPEC TS_Fifo1 = FROM VALID_TNM TO VALID_TNM  TS_Ads_00/2;

 

This reduced the amount of timing errors considerably, but there are still paths somewhere deep inside FIFO, which are not covered.

For example:
Source: ....../ADC_FIFO0/BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_6

Destination:/ADC_FIFO0/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i

and so on


I have located failed paths in the FPGA editor, and from what I've seen, these paths do not have any connection to 'wr_en' input, and that is why my multicycle constraint fails to cover them.

Is it actually possible to create a multicycle constraint for CoreGen fifo? How can I relax timing constrains for it?
Or should I generate slower clock syncronous to ADC clock using DCM and use that clock to drive the 'wr_clk' of the fifo?
I'm lost.

0 Kudos
1 Solution

Accepted Solutions
Contributor
Contributor
15,659 Views
Registered: ‎09-10-2008

Re: Asynchronous FIFO multicycle timing constraints. Is it actually possible?

Jump to solution

A short update:

 

It turned out later, that I used fifo_full signal on the read side of the FIFO.

Since fifo_full is syncronous to the write side of the FIFO, all those timing violations came out.

0 Kudos
5 Replies
Scholar golson
Scholar
13,203 Views
Registered: ‎04-07-2008

Re: Asynchronous FIFO multicycle timing constraints. Is it actually possible?

Jump to solution

Hi,

  I don't think it is a matter of your clock speed you are using.  I have had similar problems with FIFOs internal signals

not meeting timing.  I recommend looking at this Answer Record to come up with your solution:

 

http://www.xilinx.com/support/answers/30029.htm

 

 

0 Kudos
Contributor
Contributor
13,184 Views
Registered: ‎09-10-2008

Re: Asynchronous FIFO multicycle timing constraints. Is it actually possible?

Jump to solution

Hi Golson,

thank you for the prompt answer.

I have read the AR you referred to and tried to apply the constraints described there, but I think the problem is somewhere else,because:

 

1)I tried to apply the constrains from the AR #30029 as is, but got the following ERROR:

"*BU2/U0/as.fgas/normgen.flblk/clkmod/cx.wrx/pntr_gc_x(*)" does not match any design objects.

 

I then looked into the design with FPGA editor and found no signals with such names. Moreover, there are no such hieararchies like 'as.fgas' and 'normgen.flblk'.

So, I guess that FIFO in the AR was generated for different architecture(Virtex maybe?)

 

2)I then found some timing constraints in my ucf that I forgot to mention in the first post:

NET "*adc_dma_plb_0/USER_LOGIC_I/adc_int_inst/*wr_pntr_gc*" TIG;

NET "*adc_dma_plb_0/USER_LOGIC_I/adc_int_inst/*rd_pntr_gc*" TIG;

These ase the constraints from FIFO Generator v4.4 User Guide (page.91. Setup and Hold time Violations), and I think, they should take care of the problem.

 

3)This design actually worked with the speed I need before, although the maximum frequency I can achieve depends havily on how big the rest of design is.

At the beginning of this project, when I only had ADC deserializer and async FIFOs, I was able to place it with 280Mhz, then it became 210MHz, now, after I added Microblaze,it is 140MHz, although the FPGA is only 40% full.

 

Any other idea of what might cause these timing violations?

0 Kudos
Scholar golson
Scholar
13,163 Views
Registered: ‎04-07-2008

Re: Asynchronous FIFO multicycle timing constraints. Is it actually possible?

Jump to solution

Hi,

  I think you need to add some more signals to Timing Ignore (TIG)

 

According to your output you are getting these for example

 

For example:
Source: ....../ADC_FIFO0/BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_6

Destination:/ADC_FIFO0/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i

 

Plus additional

 

Maybe you can find these signals in FPGA Editor and develop constraints for them.

 

I think you need to constrain the Destination.

 

 

0 Kudos
Contributor
Contributor
13,150 Views
Registered: ‎09-10-2008

Re: Asynchronous FIFO multicycle timing constraints. Is it actually possible?

Jump to solution

I think I made it!!:) At least it routes now...

 

I followed your advice, and located all sources for the 'ram_full' signal, created
the following timing groups:

NET "*adc_dma_plb_0/*rd_pntr_bin*" TNM = RD_PNTR;
NET "*adc_dma_plb_0/*ram_full*"    TNM = RAM_full;


,and constrained them with FROM-TO constaint:
TIMESPEC TS_Fifo2 = FROM RD_PNTR TO RAM_full 8 ns;

I have tried to place and route it with 250MHz and it finished without errors, so far so good.

I have doubts though. The  Timing Analyser shows that none of these paths cross clock domains. 

What if they all were valid? 

Sure, if you add enough paths to TIG group, everything will route.:)

I will try tomorrow if the design actually works in hardware an recieves valid data.

Thank you for the hint!

0 Kudos
Contributor
Contributor
15,660 Views
Registered: ‎09-10-2008

Re: Asynchronous FIFO multicycle timing constraints. Is it actually possible?

Jump to solution

A short update:

 

It turned out later, that I used fifo_full signal on the read side of the FIFO.

Since fifo_full is syncronous to the write side of the FIFO, all those timing violations came out.

0 Kudos