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Mentor
Mentor
9,070 Views
Registered: ‎10-07-2011

Asynchronous inter-clock paths failed to meet timing

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Hi folks,

 

I'm using Vivado 2016.4 on Win10-64. I have a project that is fully implementing but timing closure is not achieved.

 

My design is using 3 clocks: AXI (200MHxz), AXILITE (50MHz) and AXIS (150MHz). AXI and AXILITE are out of the same PLL and are phase-aligned. AXIS is from another oscillator and is totally unrelated to the other 2. The clocks are reported as below:

 

ClockSummary.png

 

And I added the constraint below:

 

set_clock_groups -asynchronous -group [get_clocks {clk_fpga_0 clk_fpga_1}] \
                               -group [get_clocks SYS_CLOCK_P_D18]

 

I'm not getting any warning regarding the above constraint so I assume it is OK. The timing analysis reports the following:

 

Inter-ClockPaths.png

 

Most of the failing paths are inter-clock paths (AXIS to AXILITE and vice-versa) that should be handled by the above set_clock_group constraint. The worst failing path is as below:

Timing.png

 

Looking at the path on the device, I can see that the source and destination flops are on neighbor slices. The net is point-to-point. The source (bottom) flop is driving a SINGLE load.

ZoomedView.png

 

The entire path (route) is going all around the device, as shown below.

FullView2.png

 

Why is the router doing such a bad job?

 

I understand I could add a set_false_path constraint on that net, but I thought the above set_clock_groups constraint would do the job. Why isn't it??? Why is the timing analyzer still focussing on these async paths?

 

Thanks!

 

Claude

 

1 Solution

Accepted Solutions
Highlighted
Guide
Guide
13,903 Views
Registered: ‎01-23-2009

Two things:

 

In the get_clocks commands in the set_clock_groups command you need to use the -include_generated_clocks option - this

 

set_clock_groups -asynchronous -group [get_clocks {clk_fpga_0 clk_fpga_1}] \
                               -group [get_clocks -include_generated_clocks SYS_CLOCK_P_D18]

 

This will do what you are asking for; extend the clock group to include the clocks generated by the PLL.

 

BUT

 

I will issue my standard warning; using the set_clock_groups is an inherently dangerous command. You clearly have clock crossing paths between these domains, and hence the paths need clock domain crossing (CDC) circuits. Most CDC circuits need constraints to function properly; generally a set_max_delay -datapath_only. However, if you put the clocks in asynchronous groups, they cannot be constrained - the set_clock_groups is the highest priority constraint and will override any others. This leaves your CDCs underconstrained an open to potential system failure.

 

Take a look at this post on constraining CDCs and the posts referenced within.

 

Avrum

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7 Replies
Highlighted
Guide
Guide
13,904 Views
Registered: ‎01-23-2009

Two things:

 

In the get_clocks commands in the set_clock_groups command you need to use the -include_generated_clocks option - this

 

set_clock_groups -asynchronous -group [get_clocks {clk_fpga_0 clk_fpga_1}] \
                               -group [get_clocks -include_generated_clocks SYS_CLOCK_P_D18]

 

This will do what you are asking for; extend the clock group to include the clocks generated by the PLL.

 

BUT

 

I will issue my standard warning; using the set_clock_groups is an inherently dangerous command. You clearly have clock crossing paths between these domains, and hence the paths need clock domain crossing (CDC) circuits. Most CDC circuits need constraints to function properly; generally a set_max_delay -datapath_only. However, if you put the clocks in asynchronous groups, they cannot be constrained - the set_clock_groups is the highest priority constraint and will override any others. This leaves your CDCs underconstrained an open to potential system failure.

 

Take a look at this post on constraining CDCs and the posts referenced within.

 

Avrum

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Mentor
Mentor
9,057 Views
Registered: ‎10-07-2011

Hi Avrum,

 

Many thanks for the reply and also for providing the reference link about CDC. I'll definitely go through that.

 

Adding the -include_generated_clock resolved the issue. The timing analysis no longer reports inter-clock error, and the crazy routing is gone as well.

 

The nets that I'm sending across clock domains are single-bit STROBE and ACK. Each are going through 2 synchronizing flops. There is no other signals involved. These are basically translating a pulsed IRQ signal from the AXIS domain into level signals on the AXILITE  that can be handled by the interrupt controller and my own system registers.

 

The report_cdc command returns the following:

CDC Report

Severity  Source Clock              Destination Clock         CDC Type                 Exceptions           Endpoints  Safe  Unsafe  Unknown  No ASYNC_REG 
--------  ------------------------  ------------------------  -----------------------  -------------------  ---------  ----  ------  -------  ------------ 
Critical  AXIS_ACLK_ClockGenerator  clk_fpga_0                No Common Primary Clock  Asynch Clock Groups         17     9       8        0             0 
Critical  clk_fpga_1                clk_fpga_0                No Common Primary Clock  False Path                  94     6       0       88             0 
Critical  clk_fpga_0                clk_fpga_1                No Common Primary Clock  False Path                  90     6       0       84             0 
Warning   clk_fpga_0                AXIS_ACLK_ClockGenerator  No Common Primary Clock  Asynch Clock Groups         43    43       0        0             0 
Warning   clk_fpga_1                AXIS_ACLK_ClockGenerator  No Common Primary Clock  Asynch Clock Groups          5     5       0        0             2 
Warning   AXIS_ACLK_ClockGenerator  clk_fpga_1                No Common Primary Clock  Asynch Clock Groups          3     3       0        0             2 

 

So, the bottom 2 lines of the above table says that all AXIS/AXILITE endpoints are safe. However, I'm puzzled by the CRITICAL mention at the beginning of the first 3 lines... The clk_fpga_0 (AXI 200MHz) is only used for Xilinx IPs (VDMA, AXI Interconnect, ZYNQ PS HP0, DDR). Any comment on this?

 

Thanks for helping!

 

Claude

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Highlighted
Guide
Guide
9,043 Views
Registered: ‎01-23-2009

You could try using the -details option of the report_cdc command to determine why...

 

But one possible reason is if you are using the AXI infrastructure to cross between different clock domains. The AXI infrastructure can do clock crossing, but the CDC circuits in these blocks require constraints (they are multi-bit). The IP will have the proper constraints for the CDC, but your set_clock_groups will override these constraints, leaving the paths unconstrained. The report_cdc would see this as a failure.

 

Also, your original set_clock_groups command put clk_fpga_0 and clk_fpga_1 in the same group (typically this means that you consider these clocks as related). But the tools see these as asynchronous clock crossings with false path constraints. So there is some inconsistency there...

 

Avrum

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Mentor
Mentor
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Registered: ‎10-07-2011

I'm NOT using the AXI Infrastructure IP, unless it is embedded in some other IP that I'm using.

 

Both clk_fpga_0 and clk_fpga_1 are out of the same PLL (out of the ZYNQ PS), as shown below. So, they are both generated from the same oscillator. But it seems Vivado thinks these are 2 unrelated clocks. Why is that? How to tell Vivado these are related. use create_generated_clock with proper multiply/divide ratios?

 

Capture.PNG

 

The report_cdc -details follows. All CRITICAL paths are from VDMA to VDMA. Hence, I feel like like there is nothing I can do. Am I wrong?

CDC Report

ID      Severity  Count  Description
------  --------  -----  -------------------------------------------------------
CDC-2   Warning       4  1-bit synchronized with missing ASYNC_REG property
CDC-3   Info         41  1-bit synchronized with ASYNC_REG property
CDC-4   Critical     12  Multi-bit unknown CDC circuitry
CDC-6   Warning       2  Multi-bit synchronized with ASYNC_REG property
CDC-9   Info          1  Asynchronous reset synchronized with ASYNC_REG property
CDC-13  Critical      8  1-bit CDC path on a non-FD primitive

Source Clock: clk_fpga_0
Destination Clock: AXIS_ACLK_ClockGenerator
CDC Type: No Common Primary Clock

Row  ID     Severity  Description                                              Depth  Exception            Source (From)                                                                                                                                                                                                  Destination (To)
---  -----  --------  -------------------------------------------------------  -----  -------------------  -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------  ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  1  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                                         U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  2  CDC-6  Warning   Multi-bit synchronized with ASYNC_REG property               2  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR/VIDEO_REG_I/GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.VIDREGISTER_I/vsize_vid_reg[12:0]/C                                                               U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[12:0]/D
  3  CDC-9  Info      Asynchronous reset synchronized with ASYNC_REG property      2  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg/C                                                                                                     U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg1_reg/PRE
  4  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                                                                      U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
  5  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.S2MM_HALTED_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                                        U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.S2MM_HALTED_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  6  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.S2MM_PRM_UPDT_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                                                      U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.S2MM_PRM_UPDT_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
  7  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  8  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C     U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  9  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                 U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
 10  CDC-6  Warning   Multi-bit synchronized with ASYNC_REG property               2  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR/VIDEO_REG_I/GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.VIDREGISTER_I/vsize_vid_reg[12:0]/C                                                           U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12:0]/D
 11  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                                                                      U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
 12  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                                                                U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
 13  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_IDLE_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                                               U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_IDLE_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
 14  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                                                              U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
 15  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_RESET_FOR_ASYNC.AXIS_RESET_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                                            U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_RESET_FOR_ASYNC.AXIS_RESET_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
 16  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                                                                U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
 17  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_IDLE_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                                               U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_IDLE_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
 18  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                                                              U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
 19  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   4  Asynch Clock Groups  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_RESET_FOR_ASYNC.AXIS_RESET_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                                            U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_RESET_FOR_ASYNC.AXIS_RESET_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D

Source Clock: clk_fpga_1
Destination Clock: AXIS_ACLK_ClockGenerator
CDC Type: No Common Primary Clock

Row  ID     Severity  Description                                         Depth  Exception            Source (From)                                                    Destination (To)
---  -----  --------  --------------------------------------------------  -----  -------------------  ---------------------------------------------------------------  ----------------------------------------------------------
  1  CDC-2  Warning   1-bit synchronized with missing ASYNC_REG property      2  Asynch Clock Groups  U3/IRQManager_i/G1[0].U4/FSM1_reg[ACK]/C                         U3/IRQManager_i/G1[0].U3/G1.QD_reg[1]/D
  2  CDC-2  Warning   1-bit synchronized with missing ASYNC_REG property      2  Asynch Clock Groups  U3/IRQManager_i/G1[1].U4/FSM1_reg[ACK]/C                         U3/IRQManager_i/G1[1].U3/G1.QD_reg[1]/D
  3  CDC-3  Info      1-bit synchronized with ASYNC_REG property              2  Asynch Clock Groups  U3/reset_manage_i/stretch_sync_2_aresetlite/i_data_long_d_reg/C  U3/reset_manage_i/stretch_sync_2_aresetlite/i_data_d_reg/D
  4  CDC-3  Info      1-bit synchronized with ASYNC_REG property              2  Asynch Clock Groups  U3/reset_manage_i/stretch_sync_2_strob/i_data_long_d_reg/C       U3/reset_manage_i/stretch_sync_2_strob/i_data_d_reg/D
  5  CDC-3  Info      1-bit synchronized with ASYNC_REG property              2  Asynch Clock Groups  U3/stretch_sync_2_bypass/i_data_long_d_reg/C                     U3/stretch_sync_2_bypass/i_data_d_reg/D

Source Clock: AXIS_ACLK_ClockGenerator
Destination Clock: clk_fpga_0
CDC Type: No Common Primary Clock

Row  ID      Severity  Description                                 Depth  Exception            Source (From)                                                                                                                                                                                                                                                              Destination (To)
---  ------  --------  ------------------------------------------  -----  -------------------  -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------  -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  1  CDC-3   Info      1-bit synchronized with ASYNC_REG property      4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                                                                                             U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  2  CDC-13  Critical  1-bit CDC path on a non-FD primitive            0  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_rd_rst_reg[0]/C                            U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST
  3  CDC-13  Critical  1-bit CDC path on a non-FD primitive            0  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_rd_rst_reg[0]/C                            U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST
  4  CDC-13  Critical  1-bit CDC path on a non-FD primitive            0  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_rd_rst_reg[0]/C                            U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST
  5  CDC-13  Critical  1-bit CDC path on a non-FD primitive            0  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_rd_rst_reg[0]/C                            U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST
  6  CDC-13  Critical  1-bit CDC path on a non-FD primitive            0  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_rd_rst_reg[0]/C                            U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST
  7  CDC-3   Info      1-bit synchronized with ASYNC_REG property      4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                                                                                                                                        U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
  8  CDC-3   Info      1-bit synchronized with ASYNC_REG property      4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                                                                                                       U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  9  CDC-3   Info      1-bit synchronized with ASYNC_REG property      4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR/I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                                                       U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR/I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
 10  CDC-3   Info      1-bit synchronized with ASYNC_REG property      4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                                                                                      U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
 11  CDC-13  Critical  1-bit CDC path on a non-FD primitive            0  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_wr_rst_reg[0]/C  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST
 12  CDC-13  Critical  1-bit CDC path on a non-FD primitive            0  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_wr_rst_reg[0]/C  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST
 13  CDC-13  Critical  1-bit CDC path on a non-FD primitive            0  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_wr_rst_reg[0]/C  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST
 14  CDC-3   Info      1-bit synchronized with ASYNC_REG property      4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                                                                                                                                   U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
 15  CDC-3   Info      1-bit synchronized with ASYNC_REG property      4  Asynch Clock Groups  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                                                                                                                                        U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
 16  CDC-3   Info      1-bit synchronized with ASYNC_REG property      4  Asynch Clock Groups  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_MIN_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                                                                                                            U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_MIN_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
 17  CDC-3   Info      1-bit synchronized with ASYNC_REG property      4  Asynch Clock Groups  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_MIN_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                                                                                                            U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.AXIS_MIN_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D

Source Clock: clk_fpga_1
Destination Clock: clk_fpga_0
CDC Type: No Common Primary Clock

Row  ID     Severity  Description                                 Depth  Exception   Source (From)                                                                                                                                                                                 Destination (To)
---  -----  --------  ------------------------------------------  -----  ----------  --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------  -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  1  CDC-3  Info      1-bit synchronized with ASYNC_REG property      4  False Path  U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C  U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
  2  CDC-3  Info      1-bit synchronized with ASYNC_REG property      4  False Path  U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.LITE_WVALID_S2MM_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C  U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.LITE_WVALID_S2MM_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
  3  CDC-4  Critical  Multi-bit unknown CDC circuitry                 0  False Path  U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_rdaddr_captured_reg[7:2]/C                                                                                     U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7:2]/D
  4  CDC-4  Critical  Multi-bit unknown CDC circuitry                 0  False Path  U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_rdaddr_captured_reg[7:2]/C                                                                                     U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[7:2]/D
  5  CDC-4  Critical  Multi-bit unknown CDC circuitry                 0  False Path  U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wraddr_captured_reg[7:2]/C                                                                                     U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7:2]/D
  6  CDC-4  Critical  Multi-bit unknown CDC circuitry                 0  False Path  U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wraddr_captured_reg[7:2]/C                                                                                     U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[7:2]/D
  7  CDC-4  Critical  Multi-bit unknown CDC circuitry                 0  False Path  U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/wdata_reg[31:0]/C                                                                                                     U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[31:0]/D
  8  CDC-4  Critical  Multi-bit unknown CDC circuitry                 0  False Path  U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/wdata_reg[31:0]/C                                                                                                     U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[31:0]/D
  9  CDC-3  Info      1-bit synchronized with ASYNC_REG property      4  False Path  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                               U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
 10  CDC-3  Info      1-bit synchronized with ASYNC_REG property      4  False Path  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                           U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
 11  CDC-3  Info      1-bit synchronized with ASYNC_REG property      4  False Path  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                               U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
 12  CDC-3  Info      1-bit synchronized with ASYNC_REG property      4  False Path  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C                           U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D

Source Clock: AXIS_ACLK_ClockGenerator
Destination Clock: clk_fpga_1
CDC Type: No Common Primary Clock

Row  ID     Severity  Description                                         Depth  Exception            Source (From)                                             Destination (To)
---  -----  --------  --------------------------------------------------  -----  -------------------  --------------------------------------------------------  ---------------------------------------------------
  1  CDC-2  Warning   1-bit synchronized with missing ASYNC_REG property      2  Asynch Clock Groups  U3/IRQManager_i/G1[0].U1/FSM1_reg[STROBE]/C               U3/IRQManager_i/G1[0].U2/G1.QD_reg[1]/D
  2  CDC-2  Warning   1-bit synchronized with missing ASYNC_REG property      2  Asynch Clock Groups  U3/IRQManager_i/G1[1].U1/FSM1_reg[STROBE]/C               U3/IRQManager_i/G1[1].U2/G1.QD_reg[1]/D
  3  CDC-3  Info      1-bit synchronized with ASYNC_REG property              2  Asynch Clock Groups  U3/reset_manage_i/stretch_sync_2_ack/i_data_long_d_reg/C  U3/reset_manage_i/stretch_sync_2_ack/i_data_d_reg/D

Source Clock: clk_fpga_0
Destination Clock: clk_fpga_1
CDC Type: No Common Primary Clock

Row  ID     Severity  Description                                 Depth  Exception   Source (From)                                                                                                                                                     Destination (To)
---  -----  --------  ------------------------------------------  -----  ----------  ----------------------------------------------------------------------------------------------------------------------------------------------------------------  ---------------------------------------------------------------------------------------------------------------------------------------------------------------
  1  CDC-4  Critical  Multi-bit unknown CDC circuitry                 0  False Path  U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31:0]/C                 U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[31:0]/D
  2  CDC-4  Critical  Multi-bit unknown CDC circuitry                 0  False Path  U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31:0]/C                 U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[31:0]/D
  3  CDC-4  Critical  Multi-bit unknown CDC circuitry                 0  False Path  U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I/ptr_ref_i_reg[4:0]/C                                                                                    U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4:0]/D
  4  CDC-4  Critical  Multi-bit unknown CDC circuitry                 0  False Path  U2/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I/I_DMA_REGISTER/MM2S_ERR_FOR_IRQ.frm_store_i_reg[4:0]/C                                                  U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4:0]/D
  5  CDC-4  Critical  Multi-bit unknown CDC circuitry                 0  False Path  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I/ptr_ref_i_reg[4:0]/C                                                                                    U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4:0]/D
  6  CDC-4  Critical  Multi-bit unknown CDC circuitry                 0  False Path  U2/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I/I_DMA_REGISTER/S2MM_ERR_FOR_IRQ.frm_store_i_reg[4:0]/C                                                  U2/axi_vdma_0/U0/AXI_LITE_REG_INTERFACE_I/GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4:0]/D
  7  CDC-3  Info      1-bit synchronized with ASYNC_REG property      4  False Path  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                   U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
  8  CDC-3  Info      1-bit synchronized with ASYNC_REG property      4  False Path  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.LITE_IDLE_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.LITE_IDLE_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  9  CDC-3  Info      1-bit synchronized with ASYNC_REG property      4  False Path  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                 U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
 10  CDC-3  Info      1-bit synchronized with ASYNC_REG property      4  False Path  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                   U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D
 11  CDC-3  Info      1-bit synchronized with ASYNC_REG property      4  False Path  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.LITE_IDLE_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from/C  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.LITE_IDLE_CDC_I/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
 12  CDC-3  Info      1-bit synchronized with ASYNC_REG property      4  False Path  U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from/C                 U2/axi_vdma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I/GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to/D

 

From your comments, I understand that it may be dangerous to use the set_clock_groups -async constraint. Does that mean I should use false paths instead? I'm in the process of adding ASYNC_REG property to the synchronization register cells. Is the ASYNC_REG propertyalleviating the need for other timing constraints like set_false_path or others?

 

Claude

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Guide
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Both clk_fpga_0 and clk_fpga_1 are out of the same PLL (out of the ZYNQ PS), as shown below. So, they are both generated from the same oscillator. But it seems Vivado thinks these are 2 unrelated clocks. Why is that? How to tell Vivado these are related. use create_generated_clock with proper multiply/divide ratios?

 

So, to be honest with you, I don't know...

 

Where did the create_clock commands for these two clocks come from? Were they generated by IP Integrator, or did you declare them in your user .xdc file? If you did them manually, then try removing the definitions and see what the IP Integrator did for them...

 

As they are currently defined, they are separate primary clocks.

 

We have to understand that the report_cdc is not based on static timing analysis (STA). The rules of STA using SDC/XDC are clear - there is no such concept as unrelated clocks - all clocks are related by default (this is a mantra in Vivado). So even though these two clocks are independently declared primary clocks, they are related by default. Since they come from the same source with little or no skew, this is what we want for STA (i.e. we don't need any exceptions between them). So they will be timed synchronously (and likely pass).

 

[EDIT: NOTE AND WARNING! This is NOT correct - apparently the clocks coming from the PS should NOT be treated as synchronous clocks - see this post on the PS clocks for further information]

 

[As an aside, if there is some uncertainty between them, then this can be constrained using the set_clock_uncertainty command with the -from and -to options]

 

Unlike (for example) UCF, where clocks are unrelated by default, there is a specific syntax for relating them. This is not true in SDC/XDC, they are always related, but you can put exceptions on them. Your idea of trying to create one as a generated clock is

  a) unnecessary for STA (since they are already related) and

  b) illegal. For a clock to be a generated clock, the -source clock must be in the propagation path of the generation point - this is not the case for these two clocks (since they both exit the same block - the PS - independently)

 

All this to say, that the clocks are as "related" as they can be...

 

But, clearly, the mechanism that report_cdc uses to determine if a CDC is required between two clocks works differently - it has nothing to do with whether the clocks are "related" or not according to STA. It is correctly determining that these two have "no common primary clock", but as they are synchronous, there doesn't need to be a CDC between them...

 

That being said, the paths between them are being declared false (according to the report_cdc). From the names, at least some of these are in the DMA modules - presumably between the AXI_LITE clock to the real AXI clock. Within the DMA, these can be asynchronous clocks, and maybe the IP always assumes they are asynchronous (even if they are related like they are now) - but even so, they shouldn't be declared false; they should be covered by some other exception (set_max_delay -datapath_only).

 

And that may be the root of it. If there is an exception on the path, then even if the clocks were synchronous, they must now have a CDC between them; the exception overrides the normal synchronous timing checks so now it is possible to violate the setup/hold check of the receiving FF (hence a CDC is required).

 

Avrum

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I just found the following, going through the "Constraints User Guide" [UG903 (v2016.4) November 30, 2016, page 126].


Constraining Asynchronous Signals
The set_max_delay command can also be used to constrain asynchronous signals that do not have a clock relationship, but which require maximum delay.
For example, timing paths between two asynchronous clock domains can be disabled with the set_clock_groups command (recommended) or the set_false_path command (not recommended).

 

I maybe be taking this a little bit out-of-context, but it's getting confusing. What could qualify as asynchronous signal within the scope of the above excerpts? Two totally idependant modules, each with its own clock and with absolutely no nets crossing to one another?

 

I guess at the end the question is: What is the use-case for the set_clock_group constraint?

 

Cheers!

 

Claude

 

 

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For example, timing paths between two asynchronous clock domains can be disabled with the set_clock_groups command (recommended) or the set_false_path command (not recommended).

 

I disagree with this statement for a couple of reasons.

 

First, the set_clock_groups is no better or worse than the set_false_path command (between clocks). They both accomplish the same things - disabling timing checks on all paths between the two clocks (in the case of set_clock_groups it is in both directions, whereas the set_false_path command needs to be done twice; once in each direction). So, I presume the "recommended" is simply because you disable both directions in one command.

 

By I have argued (quite often) that you almost never want to do this...

 

First...

 

Two totally independant modules, each with its own clock and with absolutely no nets crossing to one another?

 

This needs no exceptions. If there are no nets there are no paths, hence no timing checks, hence  nothing to disable.

 

So this command is only needed if there are paths between clocked elements on the different clocks. Given that is the case, under what conditions can you declare these paths false? First of all, they all must have some kind of clock domain crossing (CDC) circuit on them. So when can you declare the clock-to-clock path within a CDC false? Pretty much the only answer is "when the signal crossing the domain is a slow changing single bit (not a bus) signal". Any other CDC must have constraints.

 

For all other CDCs some mechanism of limiting the skew (and maybe latency) on the clock domain crossing is necessary. Historically (in Vivado) this was done with set_max_delay -datapath_only. This constraint has lower priority than the set_clock_groups, so you cannot use both (the set_clock_groups wins).

 

In the newest versions of Vivado (2016.3 or so) there is a new command "set_bus_skew". This is a new mechanism for limiting the bus skew. It is explicitly created for CDCs (just look at "help set_bus_skew"). In the description it says:

 

"     Example uses of the bus skew constraint include
       clock domain crossing for gray-coded pointers, MUX-controlled and MUX-data
       holding CDC buses."

 

It also explicitly states that this is not a conventional path exception, and hence is "exempt" from the priority rules that cover other exceptions. As stated:

 

    "Note: Bus skew constraints are not overridden by clock groups, max delay,
     or false path, because set_bus_skew is a constraint between the signals of
     a bus, rather than on a particular path."

 

As a result, it is probably now acceptable to do a set_clock_groups command between clocks and use a set_bus_skew to constrain the skew explicitly. However, I am not sure how much I like this approach:

  - it does not constrain the latency of the CDC. This is rarely "critical", but I don't like the idea that it is open ended

  - this is not "standard" SDC - I am more comfortable with the set_max_delay -datapath_only solution

     - (although it is worth pointing out that the -datapath_only is also not standard SDC - it was added by Xilinx - but it is well proven and more mature)...

 

Avrum