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a.gamez
Adventurer
Adventurer
300 Views
Registered: ‎05-12-2016

BRAM not meeting timing

How one would go about getting this AXI BRAM module to meet timing? It seems that the biggest delay is inside AXI protocol routing that belongs to the IP core, so I can really touch inside that. It should run at 5ns = 200MHz, which is well below the maximum rate of BRAM, as I understand it.

Thanks!

Paths for end point u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/u_axi4_read/m_axi_rdata[31]_dff_25_14 (SLICE_X103Y62.A6), 85 paths 
 -------------------------------------------------------------------------------- 
 Slack (setup path):     -0.709ns (requirement - (data path - clock path skew + uncertainty)) 
   Source:               u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/gen_BRAM_L15.u_blk_mem_0/U0/xst_blk_mem_generator/gaxibmg.axi_blk_mem_gen/valid.cstr/ramloop[138].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (RAM) 
   Destination:          u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/u_axi4_read/m_axi_rdata[31]_dff_25_14 (FF) 
   Requirement:          5.000ns 
   Data Path Delay:      5.297ns (Levels of Logic = 3) 
   Clock Path Skew:      -0.377ns (0.998 - 1.375) 
   Source Clock:         s_processing_clk_c rising at 0.000ns 
   Destination Clock:    s_processing_clk_c rising at 5.000ns 
   Clock Uncertainty:    0.035ns 
  
   Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
     Total System Jitter (TSJ):  0.070ns 
     Total Input Jitter (TIJ):   0.000ns 
     Discrete Jitter (DJ):       0.000ns 
     Phase Error (PE):           0.000ns 
  
   Maximum Data Path at Slow Process Corner: u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/gen_BRAM_L15.u_blk_mem_0/U0/xst_blk_mem_generator/gaxibmg.axi_blk_mem_gen/valid.cstr/ramloop[138].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram to u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/u_axi4_read/m_axi_rdata[31]_dff_25_14 
     Location             Delay type         Delay(ns)  Physical Resource 
                                                        Logical Resource(s) 
     -------------------------------------------------  ------------------- 
     RAMB36_X0Y3.DOBDO6   Trcko_DOB             1.800   u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/gen_BRAM_L15.u_blk_mem_0/U0/xst_blk_mem_generator/gaxibmg.axi_blk_mem_gen/valid.cstr/ramloop[138].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram 
                                                        u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/gen_BRAM_L15.u_blk_mem_0/U0/xst_blk_mem_generator/gaxibmg.axi_blk_mem_gen/valid.cstr/ramloop[138].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram 
     SLICE_X17Y25.C4      net (fanout=1)        0.895   u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/gen_BRAM_L15.u_blk_mem_0/U0/xst_blk_mem_generator/gaxibmg.axi_blk_mem_gen/valid.cstr/ramloop[138].ram.ram_doutb<6> 
     SLICE_X17Y25.C       Tilo                  0.043   u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/gen_BRAM_L15.u_blk_mem_0/U0/xst_blk_mem_generator/gaxibmg.axi_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_1269 
                                                        u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/gen_BRAM_L15.u_blk_mem_0/U0/xst_blk_mem_generator/gaxibmg.axi_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_1269 
     SLICE_X103Y32.C5     net (fanout=1)        1.496   u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/gen_BRAM_L15.u_blk_mem_0/U0/xst_blk_mem_generator/gaxibmg.axi_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_1269 
     SLICE_X103Y32.CMUX   Tilo                  0.244   u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/gen_BRAM_L15.u_blk_mem_0/U0/xst_blk_mem_generator/gaxibmg.axi_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_1023 
                                                        u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/gen_BRAM_L15.u_blk_mem_0/U0/xst_blk_mem_generator/gaxibmg.axi_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_623 
                                                        u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/gen_BRAM_L15.u_blk_mem_0/U0/xst_blk_mem_generator/gaxibmg.axi_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_f7_22 
     SLICE_X103Y62.A6     net (fanout=1)        0.810   u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/gen_BRAM_L15.u_blk_mem_0/U0/xst_blk_mem_generator/gaxibmg.axi_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux_5_f723 
     SLICE_X103Y62.CLK    Tas                   0.009   u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/u_axi4_read/m_axi_rdata[31]_dff_25<14> 
                                                        u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/gen_BRAM_L15.u_blk_mem_0/U0/xst_blk_mem_generator/gaxibmg.axi_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe<6>23 
                                                        u_art_cap_rx_chains/u_chain/gen_mtd.u_art_mtd/u_axi4_reorder/u_axi4_read/m_axi_rdata[31]_dff_25_14 
     -------------------------------------------------  --------------------------- 
     Total                                      5.297ns (2.096ns logic, 3.201ns route) 
                                                        (39.6% logic, 60.4% route) 
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adem369
Contributor
Contributor
223 Views
Registered: ‎02-18-2019

I did not undestand where is the problem in your design, because the details you gave is not enough, I belive. But, since this is the intra-clock path problem, the solution (most of the time) is adding pipeline register. Xilinx IP cores have this option where required.

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