I have a PLL-DCM block in my design which creates 400MHz Clock and 100 MHz Clock signal from an 100MHz-input clock from my FPGA Board Xilinx ML506.
I am wondering how many registers/FFs the 400MHz Clock with a BUFG can drive correctly?
I have tested a simple counter with 67bits (67 FFs) with 1 input, 1 output. The 400MHz Clock with a BUFG drives correctly all FFs with timing constraints that I set inside UCF file.
If I make my counter with 68 bits, the Xilinx 10.1 reports failing timing constraint on Clock 400MHz.
Anyone has a good idea of how to use 400MHz that can drive 400 FFs? Thanks for your time and your help.
PS: My period constraints inside my UCF file
NET "USER_CLK" LOC="AH15"; # Bank 4NET "USER_CLK" TNM_NET = "USER_CLK";
TIMESPEC TS_USER_CLK = PERIOD "USER_CLK" 10 ns HIGH 50 %;NET "Clock4X" TNM_NET = "Clock4X";TIMESPEC TS_Clock4X = PERIOD "Clock4X" TS_USER_CLK / 4 HIGH 50 %;
The issue is not with the BUFG driving the destination FFs with 400MHz.
The issue is you have combinatorial paths (both logic and routing) in your 67-bit counter that exceed your 2.5ns period constraint.
See the static timing report (.twr) for more details on the failing paths.
A question like "how much logic can be driven at 400MHz" is very dependent on the type of logic (e.g. number of levels of logic), placement, routing, etc.
You may find this useful:
http://www.xilinx.com/support/documentation/white_papers/wp331.pdf (Timing Closure 6.1i)
http://www.xilinx.com/support/training/rel/timing-closure-flow.htm (Recorded Lecture: Timing Closure Flow)
== edit. I meant 68-bits