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mildred
Adventurer
Adventurer
369 Views
Registered: ‎03-22-2021

Hello,

I am having several timing problems i was wondering if it was useful to cascade several bufg?

I have a 200 MHZ clock that comes out from a bufg and is directed to several different modules, is it useful to put another bufg in front of every module?

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dsheils
Moderator
Moderator
357 Views
Registered: ‎01-05-2017

Hi @mildred 

Cascaded clock buffers are rarely a good idea. They will increase your clock insertion delay and may increase clock skew.

We would need more details on the problem you are seeing. Can you attach the timing summary report for the failing paths? Also report_methodology also.

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ghasemi_r
Explorer
Explorer
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Registered: ‎05-07-2018

No, it never help you

If you have multi domain clock, you need to use FIFO

in some cases, use :"set false path" .

some times the design need more time or it is complex, so it is better to register (pipe) some of REGs.

dsheils
Moderator
Moderator
358 Views
Registered: ‎01-05-2017

Hi @mildred 

Cascaded clock buffers are rarely a good idea. They will increase your clock insertion delay and may increase clock skew.

We would need more details on the problem you are seeing. Can you attach the timing summary report for the failing paths? Also report_methodology also.

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dpaul24
Scholar
Scholar
354 Views
Registered: ‎08-07-2014

@mildred ,

No.

You need to analyze the failing failing paths. As mentioned in the above post, double click on the failing paths the tool reports and analyze the or use the TCL commands.

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