UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Voyager
Voyager
316 Views
Registered: ‎04-12-2012

BUFGCE_DIV create_generated_clock

Jump to solution

Hello,

Does the use of a BUFGCE_DIV (clock division capable buffer) requires us to explicitly use the "create_generated_clock" for its output ? 

Or will Vivado automatically create it for us ?

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
291 Views
Registered: ‎02-27-2019

回复: BUFGCE_DIV create_generated_clock

Jump to solution

Hi @shaikon ,

Please refer to https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug903-vivado-using-constraints.pdf page90. 

In the Xilinx UltraScale™ device family, the CMBs are:

•MMCM* / PLL*

•BUFG_GT / BUFGCE_DIV

•GT*_COMMON / GT*_CHANNEL / IBUFDS_GTE3

•BITSLICE_CONTROL / RX*_BITSLICE

•ISERDESE3

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
292 Views
Registered: ‎02-27-2019

回复: BUFGCE_DIV create_generated_clock

Jump to solution

Hi @shaikon ,

Please refer to https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug903-vivado-using-constraints.pdf page90. 

In the Xilinx UltraScale™ device family, the CMBs are:

•MMCM* / PLL*

•BUFG_GT / BUFGCE_DIV

•GT*_COMMON / GT*_CHANNEL / IBUFDS_GTE3

•BITSLICE_CONTROL / RX*_BITSLICE

•ISERDESE3

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

257 Views
Registered: ‎01-22-2015

Re: BUFGCE_DIV create_generated_clock

Jump to solution

@shaikon 

As yangc has pointed out, BUFGCE_DIV is one of the UltraScale devices that produces automatically derived clocks.  When using these devices, the create_generated_clock constraint is automatically written for you.  However, this constraint is not placed in the Vivado .xdc file and is hidden from you. 

Also, when using dividing clock buffers like BUFGCE_DIV (or BUFR for 7-Series devices) in parallel, you should add an "alignment procedure" to your HDL code so that the clock outputs from the parallel buffers are in-phase.  This alignment procedure is mentioned on pg119 of UG949(v2019.2) but is not well explained.  There is more description of the alignment procedure for the BUFR on pg110 of UG472(v1.14).  However, the BUFR alignment procedure appears to be incorrect as discussed in <this> post.

Mark

Tags (1)