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Visitor
Visitor
495 Views
Registered: ‎05-30-2019

CDC 2 Flip Flop synchronizer for Zynq

Hi,

I am trying to solve a CDC error by using a 2 Flip Flop synchronizer technique as shown below. But Vivado is not recognizing it as a CDC circuit and flagging an error for the first Flip Flop which is signal1.  

attribute ASYNC_REG                    : string;                    

attribute ASYNC_REG of signal1: signal is "TRUE";

attribute ASYNC_REG of signal2: signal is "TRUE";

                CDC_sync: process(clk) begin

                                if rising_edge(clk) then

                                               signal1 <= in_signal;

                                                signal2 <= signal1;

                                end if;

                end process;

 

Thanks in advance. 

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Xilinx Employee
Xilinx Employee
472 Views
Registered: ‎05-14-2008

Re: CDC 2 Flip Flop synchronizer for Zynq

What error did you receive about signal1?

-vivian

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Visitor
Visitor
459 Views
Registered: ‎05-30-2019

Re: CDC 2 Flip Flop synchronizer for Zynq

Hi,

Thanks for the response. I get the following warning when I run report clock interaction 

NameSlackLevelsHigh FanoutFromToTotal DelayLogic DelayNet DelayLogic %Net %RequirementSource ClockDestination ClockExceptionSkew
Constrained Paths (1)
clk_1x_PLL_CLK_DDR_In (10)
Path 1-8.6744design_1_i/TopLevel_1/U0/U55/in_signal_reg/Cdesign_1_i/TopLevel_1/U0/U7/U1/signal1_reg/D3.721.152.5830.7769.230.00clk_50Mhz_PLL_40Mhzclk_1x_PLL_CLK_DDR_In -4.62
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455 Views
Registered: ‎09-17-2018

Re: CDC 2 Flip Flop synchronizer for Zynq

In Vivado,

All data crossings are assummed synchronous by default, so you must exclude the clock domain crossing path with a constraint.  Then your timing error will go away.

l.e.o.

 

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Visitor
Visitor
416 Views
Registered: ‎04-08-2018

Re: CDC 2 Flip Flop synchronizer for Zynq

As indicated by lowearthorbit, all clocks are related by default. Using sync flops with "ASYNC_REG" property would tell the tool to place the two flops in the same CLB. You still need to add a false path constraint to the signal1 flop.

Peter Kwan, Senior FPGA Engineer
Designlinx Hardware Solution, Inc
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Guide
Guide
404 Views
Registered: ‎01-23-2009

Re: CDC 2 Flip Flop synchronizer for Zynq

You still need to add a false path constraint to the signal1 flop

Careful - "You still need to add an exception to the path ending at the signal1 flop". The correct exception isn't always a "set_false_path" - depending on the characteristics of the clock domain crossing circuit, it may need to be a "set_max_delay -datapath_only"...

Avrum

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Visitor
Visitor
399 Views
Registered: ‎05-30-2019

Re: CDC 2 Flip Flop synchronizer for Zynq

Can I use XPM_CDC_SINGLE so that Vivado can recognize it as a synchronizer solution for CDC and will not flag critical warning for signal1. 

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Visitor
Visitor
377 Views
Registered: ‎04-08-2018

Re: CDC 2 Flip Flop synchronizer for Zynq

Accoring to AR# 67738, it will add false path to the receiving flop. You still need to becareful as per @avrumw  comment. 

Peter Kwan, Senior FPGA Engineer
Designlinx Hardware Solution, Inc
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