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Visitor dbrent
Visitor
244 Views
Registered: ‎02-05-2019

Can timing paths/arcs from OBUFT/O to IBUF/I be enabled?

My application has internal test logic that drives bidirectional I/Os that are inputs to the normal functional logic. This enables the test logic to detect stuck/shorted inputs. The output registers of the test logic and the input registers of the normal logic are placed in the IOBs and are clocked by separate 100MHz clock phases but Vivado will not analyze the path between them because of the automatic (set_disable_timing?) constraints imposed on OBUFT/O to IBUF/I paths/arcs by Vivado.

Thanks,

Dave Brent

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Xilinx Employee
Xilinx Employee
157 Views
Registered: ‎07-16-2008

回复: Can timing paths/arcs from OBUFT/O to IBUF/I be enabled?

A timing path starts from and ends at valid endpoints. The inout port is an endpoint. 

You can analyze timing from the output register through the OBUF/O to the port, or from the port through IBUF/I to the input register. But there's no such timing path from OBUFT/O to IBUF/I.

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Visitor dbrent
Visitor
139 Views
Registered: ‎02-05-2019

回复: Can timing paths/arcs from OBUFT/O to IBUF/I be enabled?

graces,

As I explained above, my application has a valid timing path that starts at an output (or output enable) register in an IOB, goes through the OBUFT AND IBUF in the IOB, and ends in the input register in the IOB. This path cannot be analyzed because Vivado automatically cuts the arc from the OBUFT to the IBUF. Quartus allows analysis of this arc/path to be enabled or disabled and Vivado should too.

Regards,

Dave Brent