cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
496 Views
Registered: ‎06-18-2016

Clock outputs from MIG block not constrained?

Hi All,

I'm using the ui_addn_clk_0 output from the MIG block to get a 100MHz clock for a smart connect block in the block design and for my logic. My logic is working but fails timing.  All pins connected to this 100MHz generated clock get the "no clock driven by root clock pin" message in the timing summary. When I run Report Clock Networks the name ui_addn_clk_0 clock does not show up, but a clock labeled "unconstrained" shows up and shows all the same pins that are connected to ui_addn_clk_0.

There is no occurrence of either the ui_clk or ui_addn_clk_0 output in the MIG-generated xdc file. Do I need to generate these constraints manually even though they are derived clocks?

Thanks,
Tom

 

0 Kudos
6 Replies
Highlighted
Moderator
Moderator
442 Views
Registered: ‎04-18-2011

Which device family are you targetting? In the netlist where does this clock come from inside the core? If it is coming from an mmcm I'd expect it to propagate 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
424 Views
Registered: ‎05-14-2008

The “ui_addn_clk_0” is one of the MMCM output clock. As long as you create clock constraint for the MMCM input clock (SYS_CLK of MIG), the tool will automatically add generated clock constraint for ui_addn_clk_0. 

If you report_clocks in the synthesized design or implemented design, is there a clock created for SYS_CLK?

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Adventurer
Adventurer
401 Views
Registered: ‎06-18-2016

On my system, MIG creates location and other clock constraints for sys_clk_p in the xdc file it generates, but does not create any constraints for ui_addn_clk_0. In the schematic for the MIG block, sys_clk goes through a PLL and then an MMCM from which ui_addn_clk_0 is output.

When I run report_clocks, sys_clk_p is present, and ui_addn_clk_0 is also there but only connected to the u_ila block.

Report Clock Network shows three entries (I omitted some text, couldn't do copy/paste on the report):

debug_hub......TCK
sys_clk_p 200MHz (drives 21414 loads)
Unconstrained (177 loads)

- Tom

 

0 Kudos
Highlighted
Adventurer
Adventurer
399 Views
Registered: ‎06-18-2016

It's a Zync SoC (ZC706 board). Please see the post I sent to Vivian's response for more details.

- Tom

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
382 Views
Registered: ‎05-14-2008

ui_addn_clk_0 clock constraint does not need to be in any xdc.

It is auto added by the tool in the design in memory. That's why you see it with report_clocks.

 

"When I run report_clocks, sys_clk_p is present, and ui_addn_clk_0 is also there but only connected to the u_ila block."

I don't quite understand this. What do you mean by "ui_addn_clk_0" only connected to u_ila? How do you see this with report_clocks?

Can you post the contents returned by report_clocks?

 

If report_clocks return ui_addn_clk_0, all clock pins connected to this clock should have been well constrained. Are those pins connected to ui_addn_clk_0 directly?

Is ui_addn_clk_0 the 100MHz clock you mentioned?

 

You can use get_clocks to check if a clock is defined on a certain pin.

For example, get_clocks [get_pins <pin_name>]

If you run get_clocks on the MMCM output pin that generates ui_addn_clk_0, it should return the clock's name.

And if you run get_clocks on pins that connected to this clock net, it should return the same clock name.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Adventurer
Adventurer
350 Views
Registered: ‎06-18-2016

Thanks for the explanation of ui_addn_clk_0 not needed in the xdc file.

When I said 100MHz clock I meant ui_addn_clk_0 which in my design this is also connected to diag_clk_100.

When I click on the signal ui_addn_clk_0 on the implementation schematic, in the properties window of the GUI it shows the signal name diag_clk_100 with property of global clock. diag_clk_100 is in the net list.

Here is output from get_clocks. Pins are there but no clock found for both ui_addn_clk_0 and diag_clk_100:

get_clocks [ get_pins BLOCK_DESIGN/mig_7series_0/ui_addn_clk_0]
WARNING: [Vivado 12-627] No clocks matched 'BLOCK_DESIGN/mig_7series_0/ui_addn_clk_0'.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks.

get_clocks [ get_pins BLOCK_DESIGN/diag_clk_100]
WARNING: [Vivado 12-627] No clocks matched 'BLOCK_DESIGN/diag_clk_100'.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks.

I must have been mistaken when I saw ui_addn_clk_0 in the report_clocks output because it's not there now. Report is at the end of this reply.

Here is the clock networks report:

Clock Networks Report

Constrained Clocks
-------------------

Clock sys_clk_p (200MHz)(endpoints: 21500 clock, 498 nonclock)
Port sys_clk_p

Thanks for looking into this and please let me know what other information I can provide.

- Tom

Here is the report_clocks output:

report_clocks
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
| Date : Fri Feb 28 15:41:24 2020
| Host : ratso running 64-bit Service Pack 1 (build 7601)
| Command : report_clocks
| Design : demo_top
| Device : 7z045-ffg900
| Speed File : -2 PRODUCTION 1.11 2014-09-11
------------------------------------------------------------------------------------

Clock Report


Attributes
P: Propagated
G: Generated
A: Auto-derived
R: Renamed
V: Virtual
I: Inverted
S: Pin phase-shifted with Latency mode

Clock Period(ns) Waveform(ns) Attributes Sources
sys_clk_p 5.000 {0.000 2.500} P {sys_clk_p}
clk_div2_bufg_in 2.500 {0.000 1.250} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT6}
clk_pll_i 5.000 {0.000 2.500} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT}
clk_ref_mmcm_400 2.500 {0.000 1.250} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKOUT1}
freq_refclk 1.250 {1.172 1.797} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0}
iserdes_clkdiv 2.500 {1.172 2.422} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV}
iserdes_clkdiv_1 2.500 {1.172 2.422} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLKDIV}
iserdes_clkdiv_2 2.500 {1.172 2.422} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV}
iserdes_clkdiv_3 2.500 {1.172 2.422} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV}
iserdes_clkdiv_4 2.500 {1.172 2.422} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV}
iserdes_clkdiv_5 2.500 {1.172 2.422} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLKDIV}
iserdes_clkdiv_6 2.500 {1.172 2.422} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV}
iserdes_clkdiv_7 2.500 {1.172 2.422} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV}
mem_refclk 1.250 {0.000 0.625} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1}
mmcm_clkfbout 5.000 {0.000 2.500} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKFBOUT}
mmcm_clkout0 10.000 {0.000 5.000} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0}
mmcm_clkout1 5.000 {0.000 2.500} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1}
mmcm_clkout2 5.000 {0.000 2.500} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT2}
mmcm_clkout3 5.000 {0.000 2.500} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT3}
mmcm_clkout4 5.000 {0.000 2.500} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT4}
mmcm_ps_clk_bufg_in 10.000 {0.000 5.000} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT5}
oserdes_clk 1.250 {0.000 0.625} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK}
oserdes_clk_1 1.250 {0.000 0.625} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK}
oserdes_clk_10 1.250 {0.000 0.625} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK}
oserdes_clk_2 1.250 {0.000 0.625} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK}
oserdes_clk_3 1.250 {0.000 0.625} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK}
oserdes_clk_4 1.250 {0.000 0.625} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK}
oserdes_clk_5 1.250 {0.000 0.625} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK}
oserdes_clk_6 1.250 {0.000 0.625} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK}
oserdes_clk_7 1.250 {0.000 0.625} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK}
oserdes_clk_8 1.250 {0.000 0.625} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK}
oserdes_clk_9 1.250 {0.000 0.625} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK}
oserdes_clkdiv 2.500 {0.000 1.250} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV}
oserdes_clkdiv_1 2.500 {0.000 1.250} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV}
oserdes_clkdiv_10 2.500 {0.000 1.250} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV}
oserdes_clkdiv_2 2.500 {0.000 1.250} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV}
oserdes_clkdiv_3 2.500 {0.000 1.250} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV}
oserdes_clkdiv_4 5.000 {0.000 2.500} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV}
oserdes_clkdiv_5 5.000 {0.000 2.500} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV}
oserdes_clkdiv_6 5.000 {0.000 2.500} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV}
oserdes_clkdiv_7 2.500 {0.000 1.250} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV}
oserdes_clkdiv_8 2.500 {0.000 1.250} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV}
oserdes_clkdiv_9 2.500 {0.000 1.250} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV}
pll_clk3_out 5.000 {0.000 2.500} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3}
pll_clkfbout 5.000 {0.000 2.500} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT}
sync_pulse 20.000 {0.547 1.797} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2}
u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk 1.250 {1.172 1.797} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK}
u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk 1.250 {1.172 1.797} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK}
u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.250 {1.172 1.797} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK}
u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk 1.250 {1.172 1.797} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK}
u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk 1.250 {1.172 1.797} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK}
u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk 1.250 {1.172 1.797} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK}
u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.250 {1.172 1.797} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK}
u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 1.250 {1.172 1.797} P,G,A {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK}


====================================================
Generated Clocks
====================================================

Generated Clock : clk_div2_bufg_in
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1
Master Clock : pll_clk3_out
Multiply By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT6}

Generated Clock : clk_pll_i
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1
Master Clock : pll_clk3_out
Multiply By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT}

Generated Clock : clk_ref_mmcm_400
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKIN1
Master Clock : sys_clk_p
Multiply By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKOUT1}

Generated Clock : freq_refclk
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKIN1
Master Clock : sys_clk_p
Edges : {1 2 3}
Edge Shifts(ns) : {1.172 -0.703 -2.578}
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0}

Generated Clock : iserdes_clkdiv
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK
Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV}

Generated Clock : iserdes_clkdiv_1
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK
Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLKDIV}

Generated Clock : iserdes_clkdiv_2
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK
Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV}

Generated Clock : iserdes_clkdiv_3
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK
Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV}

Generated Clock : iserdes_clkdiv_4
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK
Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV}

Generated Clock : iserdes_clkdiv_5
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK
Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLKDIV}

Generated Clock : iserdes_clkdiv_6
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK
Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV}

Generated Clock : iserdes_clkdiv_7
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK
Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV}

Generated Clock : mem_refclk
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKIN1
Master Clock : sys_clk_p
Multiply By : 4
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1}

Generated Clock : mmcm_clkfbout
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKIN1
Master Clock : sys_clk_p
Multiply By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKFBOUT}

Generated Clock : mmcm_clkout0
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1
Master Clock : pll_clk3_out
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 2.500 5.000}
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0}

Generated Clock : mmcm_clkout1
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1
Master Clock : pll_clk3_out
Multiply By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1}

Generated Clock : mmcm_clkout2
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1
Master Clock : pll_clk3_out
Multiply By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT2}

Generated Clock : mmcm_clkout3
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1
Master Clock : pll_clk3_out
Multiply By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT3}

Generated Clock : mmcm_clkout4
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1
Master Clock : pll_clk3_out
Multiply By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT4}

Generated Clock : mmcm_ps_clk_bufg_in
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1
Master Clock : pll_clk3_out
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 2.500 5.000}
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT5}

Generated Clock : oserdes_clk
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/MEMREFCLK
Master Clock : mem_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK}

Generated Clock : oserdes_clk_1
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/MEMREFCLK
Master Clock : mem_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK}

Generated Clock : oserdes_clk_10
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/MEMREFCLK
Master Clock : mem_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK}

Generated Clock : oserdes_clk_2
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/MEMREFCLK
Master Clock : mem_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK}

Generated Clock : oserdes_clk_3
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/MEMREFCLK
Master Clock : mem_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK}

Generated Clock : oserdes_clk_4
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/MEMREFCLK
Master Clock : mem_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK}

Generated Clock : oserdes_clk_5
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/MEMREFCLK
Master Clock : mem_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK}

Generated Clock : oserdes_clk_6
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/MEMREFCLK
Master Clock : mem_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK}

Generated Clock : oserdes_clk_7
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/MEMREFCLK
Master Clock : mem_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK}

Generated Clock : oserdes_clk_8
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/MEMREFCLK
Master Clock : mem_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK}

Generated Clock : oserdes_clk_9
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/MEMREFCLK
Master Clock : mem_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK}

Generated Clock : oserdes_clkdiv
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK
Master Clock : oserdes_clk
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV}

Generated Clock : oserdes_clkdiv_1
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK
Master Clock : oserdes_clk_1
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV}

Generated Clock : oserdes_clkdiv_10
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK
Master Clock : oserdes_clk_10
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV}

Generated Clock : oserdes_clkdiv_2
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK
Master Clock : oserdes_clk_2
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV}

Generated Clock : oserdes_clkdiv_3
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK
Master Clock : oserdes_clk_3
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV}

Generated Clock : oserdes_clkdiv_4
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK
Master Clock : oserdes_clk_4
Divide By : 4
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV}

Generated Clock : oserdes_clkdiv_5
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK
Master Clock : oserdes_clk_5
Divide By : 4
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV}

Generated Clock : oserdes_clkdiv_6
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK
Master Clock : oserdes_clk_6
Divide By : 4
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV}

Generated Clock : oserdes_clkdiv_7
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK
Master Clock : oserdes_clk_7
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV}

Generated Clock : oserdes_clkdiv_8
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK
Master Clock : oserdes_clk_8
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV}

Generated Clock : oserdes_clkdiv_9
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK
Master Clock : oserdes_clk_9
Divide By : 2
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV}

Generated Clock : pll_clk3_out
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKIN1
Master Clock : sys_clk_p
Multiply By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3}

Generated Clock : pll_clkfbout
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKIN1
Master Clock : sys_clk_p
Multiply By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT}

Generated Clock : sync_pulse
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKIN1
Master Clock : sys_clk_p
Edges : {1 2 3}
Edge Shifts(ns) : {0.547 -0.703 15.547}
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2}

Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/FREQREFCLK
Master Clock : freq_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK}

Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/FREQREFCLK
Master Clock : freq_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK}

Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/FREQREFCLK
Master Clock : freq_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK}

Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/FREQREFCLK
Master Clock : freq_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK}

Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/FREQREFCLK
Master Clock : freq_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK}

Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/FREQREFCLK
Master Clock : freq_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK}

Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/FREQREFCLK
Master Clock : freq_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK}

Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk
Master Source : BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/FREQREFCLK
Master Clock : freq_refclk
Divide By : 1
Generated Sources : {BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK}

 

====================================================
User Uncertainty
====================================================

 

====================================================
User Jitter
====================================================

-- END -----------------------------------------------------------------------------------------------

0 Kudos