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1keith1
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Registered: ‎02-17-2014

Configuring clock speed

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Hi, I could use some help setting up the UCF for a Serial Rapid IO IP core, particularly with the clock.

 

I am trying to modify the ucf to work with a Virtex 6 HX380T, I will include the documentation of the specific board for reference.

 

So in the example design of the rapid IO IP core a ucf is generated and they use the following code for several clock timing specs though I am guessing this doesn't need to be modified to the pins on my board since its done logically.

Here is a snippet of the UCF:

 

NET "*gt_clk" TNM_NET = gt_clk;
TIMESPEC TS_gt_clk = PERIOD "gt_clk" 4 ns HIGH 50 % PRIORITY 1;

NET "*gt_pcs_clk" TNM_NET = gt_pcs_clk;
TIMESPEC TS_gt_pcs_clk = PERIOD "gt_pcs_clk" "TS_gt_clk" * 2 HIGH 50 % PRIORITY 1;
NET "*phy_clk" TNM_NET = phy_clk;
TIMESPEC TS_phy_clk = PERIOD "phy_clk" "TS_gt_clk" * 1 HIGH 50 % PRIORITY 1;

NET "*log_clk" TNM_NET = log_clk;
TIMESPEC TS_log_clk = PERIOD "log_clk" 4 ns HIGH 50 % PRIORITY 1;

 

 

But what about the REFCLK seen below? I will have to select a pin for this from the PDF.

 

# Lock down placement of REFCLK to correlate with example GTP location
NET "sys_clkp" IOSTANDARD = LVCMOS18 | LOC = "AB6" ;
NET "sys_clkn" IOSTANDARD = LVCMOS18 | LOC = "AB5" ;

 

I don't know how to set clock speed for sys_clkp (sys_clkn is only the inverse). Looking through the pdf documentation, on page 17 I found that the DDR3 clock can be modulated:

"As illustrated by figure (), the DDR3 clock for both SODIMMs is generated by high-performance low-jitter
SI570 programmable crystal Although the default frequency value is set to 200MHz, this crystal can be
controlled by FPGA through I2C interface for different clock values.'

 

Since I don't know if any of the other clocks can be modulated on the board I will try and use the DDR3 clock.


How do I set the DDR3 clock to 125mhz for Sys_clkp? Or if you can find a better clock to use from the PDF documentation let me know.

 

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driesd
Xilinx Employee
Xilinx Employee
20,407 Views
Registered: ‎11-28-2007

Hi Keith,

 

It all depends on the settings of the GTX primitive that you configure using the GT wizard.

156.25MHz can also a reference clocks for some speeds and protocols.

 

The reason why no timing constraints are required or even useful is because there is no effect on the placer or router. The placing of GTs and routing of the clocks is fixed anyway for Gigabit Transceivers. It's not flexible like for plain fabric LUTs and registers.

 

Regarding your constraints:

NET "sys_clkp" IOSTANDARD = LVCMOS18 | LOC = "AB6" ;
NET "sys_clkn" IOSTANDARD = LVCMOS18 | LOC = "AB5" ;

 I hope this was a quick example because it is wrong: LVCMOS18 is not a differential I/O standard, but single-ended while sys_clkp/n seems to indicate a differential I/O.

 

 

Best regards

Dries

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1keith1
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Registered: ‎02-17-2014

Forgot to attach the PDF. 

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driesd
Xilinx Employee
Xilinx Employee
12,439 Views
Registered: ‎11-28-2007

Hi Keith,

 

Our Gigabit transceiver reference clocks don't require any timing constraints.

That's why the example constraints do not constrain these REFCLK pins.

 

 

Best regards

Dries

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1keith1
Participant
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Registered: ‎02-17-2014
But they will have to run at a certain speed correct? When they are connected in the example design like this:

# Lock down placement of REFCLK to correlate with example GTP location
NET "sys_clkp" IOSTANDARD = LVCMOS18 | LOC = "AB6" ;
NET "sys_clkn" IOSTANDARD = LVCMOS18 | LOC = "AB5" ;

They are assuming the clock is connected to an oscillator at 125mhz correct?
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driesd
Xilinx Employee
Xilinx Employee
20,408 Views
Registered: ‎11-28-2007

Hi Keith,

 

It all depends on the settings of the GTX primitive that you configure using the GT wizard.

156.25MHz can also a reference clocks for some speeds and protocols.

 

The reason why no timing constraints are required or even useful is because there is no effect on the placer or router. The placing of GTs and routing of the clocks is fixed anyway for Gigabit Transceivers. It's not flexible like for plain fabric LUTs and registers.

 

Regarding your constraints:

NET "sys_clkp" IOSTANDARD = LVCMOS18 | LOC = "AB6" ;
NET "sys_clkn" IOSTANDARD = LVCMOS18 | LOC = "AB5" ;

 I hope this was a quick example because it is wrong: LVCMOS18 is not a differential I/O standard, but single-ended while sys_clkp/n seems to indicate a differential I/O.

 

 

Best regards

Dries

--------------------------------------------------------------------------------------------------------------------
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View solution in original post

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