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Visitor
Visitor
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Registered: ‎09-23-2019

Confusing between timing datasheet and timing summary

 

Hi,

 

Here is my design, U31 DFF output connects to U38/39 DFF input.

IPCLK(orange, 138MHz) is ahead DBMR_CK(138MHz) by 1.6ns and U31 internal clock(blue, 138MHz) is a 90-degree shift(1.81ns) from DBMR_CK.

U38/39 DFF setup time is -0.311~0.055ns, round-up to Tsu=0.5ns.

myfingerhurt_1-1605515545219.png

I got the U31 datasheet by Vivado report _datasheet.

I highlighted the B_R_DBMR2_DQ[15] Tco_max=3.4(3.344 round-up) and Tco_min=2.5(2.527 round-down)

myfingerhurt_5-1605516383889.png

I did my own output_delay calculations based on Tco_max=3.4 and Tco_min=2.5.

Please refer to the chart down below, the down portion is based on my calculations, the up portion is based on the timing summary setup path report. 

According to my calculation, setup can't be satisfied due to the large Tco_max=3.4, slack becomes negative (-0.276).

But when I added up Vivado setup timing reports, the timing can be fit, 1.5ns slack.

Apparently, the timing report didn't use the Tco_max=3.4, but based on a smaller value.

Question: Why report_timing_summary gives a better result compared to report_datasheet, and the value is even better than Tco_min=2.5, this is so confusing. How did the Tco_max=3.4 and Tco_min=2.5 come from?

 

b: Board delay 0.1ns~0.2ns

u: Clock uncertainty 0.2ns

Max: output_delay max

Min: output_dely min

max_output_delay = Tbd_max + Tsu – Tck_dly(Tcd_min)
= 0.2 + 0.5 – (-1.6)
= 2.3

min_output_delay = Tbd_min - Th – Tck_dly(Tcd_max)
= 0.1 - 2.1 – (-1.6)
= -0.4

myfingerhurt_0-1605515427575.png

 

This is the setup path report of B_R_DBMR2_DQ[15].

myfingerhurt_4-1605515734490.png

Best regards

Ben

 

2 Replies
288 Views
Registered: ‎01-22-2015

Ben,

We don't see many people trying to understand timing analysis with such detail.  Good job!

I think the confusion stems from the definition of the report_datasheet columns called "Max Clk to Port" and "Min Clk to Port".  These values are not Tco_max and Tco_min for the register.  Instead, Clk_to_Port includes Tco and delays of OBUF and routing to the port as shown in the screenshot below.

Clk_to_Port.jpg 

So, from your path report, the Clk_to_Port time is calculated as:

      Tco + net_delay + OBUF_delay = 0.177 + 0.001 + 1.229 = 1.407.

I'm not sure why this number (1.407) is below the "Min Clk to Port" of  2.527 from your report_datasheet. 

Anyway, the timing path report is your go-to report for understanding timing analysis.  I suggest you go through your nice analysis again using numbers from the path report.

Also, your path report shows that you have a multi-cycle constraint on the path.  For now, get rid of that constraint since it is likely to confuse your learning.

Cheers,
Mark

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Visitor
Visitor
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Registered: ‎09-23-2019

markg@prosensing.com wrote:

I'm not sure why this number (1.407) is below the "Min Clk to Port" of  2.527 from your report_datasheet. 

 


Mark, thank you for replying to me.

I think I had found what I was wrong. The Tco_min/max should regard to DBMR_CK.

Here is the modified version, this time everything makes sense.

 
 

2020-11-17 16_34_56-H1937021 - リモート デスクトップ接続.png

Regards,

Ben

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