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pulsar
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Registered: ‎04-16-2015

Constraints_difficulty

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Hello all

 

I use 2 clocks for Simple Dual Port RAM IP Core components:
CLK - my own clock for writing to the RAM.
and
user_clk - clock, that I use for reading from the RAM through xilinx IP PCIexpress core.
    These clocks have to be asynchronous and have not to interact.

 

Clock CLK originates from external LVDS oscillator:
   CLK_EXTERNAL_P : in STD_LOGIC;  
   CLK_EXTERNAL_N : in STD_LOGIC;
   This clock is constrained in the user constraints file (constrs_9.xdc).


Clock user_clk I get from xilinx PCIexpess core.
   I did not constained this clock in the user constraints file and
   I did not find  clock named "user_clk" in the xilinx constaints file (xilinx_pcie_7x_ep_x8g2_VC707.xdc)

 

The VHDL design with the included xilinx reference PCIexpress core for VC707 board was sussesfully implemented
in Vivado 2015.4, but after some modifications failled in Vivado 2016.4 with the 1 critical warning:
"[Timing 38-282] The design failed to meet the timing requirements."
Intra-Clock Paths shows the
userclk2
with the Toral Violation = -152.034 ns

 

As I undesrstand this critical warning
Implementation looks clock userclk2 ( that originate from user_clk, or vice-versa)
as interactive with clock CLK.

 

As I thing my task is to explain for Implementation that
CLK and user_clk are asynchronous clocks and have not to interact.

 

I tried to use constraint
set_clock_groups -name async_clk0_clk1 -asynchronous -group {CLK_EXTERNAL_P}
(Clock CLK origanates from external LVDS clock - CLK_EXTERNAL_P and CLK_EXTERNAL_N)
But result was the same - critical warning.

 

May be someone can suggest me how to create necessary constraints.

 

Thank you.

Best regards,
Viktor
P.S.
I worked within Linux(Debian7).

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pulsar
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Registered: ‎04-16-2015

Hello Avrum

 

You was right.

It was a simple problem within one clock - userclk2

After adding one register between  BRAM's output and PCIexpress register

Implementation works  without critical warning. 

All user specified timing constraints are met.

 

Thank you very much.

 

Best regards,
Viktor

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avrumw
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Registered: ‎01-23-2009

 I did not find  clock named "user_clk" in the xilinx constaints file (xilinx_pcie_7x_ep_x8g2_VC707.xdc)

 

So, first, don't confuse the net name with the clock name. The net coming out of the PCIe block may be called user_clk, but there is nothing that says the clock is named user_clk - in fact, it is most probably called usrclk2. If you want to be sure, you can (with the synthesized or implemented design open) use the Tcl command

 

get_clocks -of_objects [get_nets usr_clk]

 

Intra-Clock Paths shows the userclk2 with the Toral Violation = -152.034 ns

 

I tried to use constraint
set_clock_groups -name async_clk0_clk1 -asynchronous -group {CLK_EXTERNAL_P}

 

 

There are two things wrong with the above.

 

First, the failing path is an Intra-clock path, which means it starts and end on the same clock (that's what intra means - inter-clock means between two clocks). Since it is not between different clocks, then the set_clock_groups doesn't have any effect on it.

 

Second (and probably more importantly) it is not valid to simply declare asynchronous clocks as different clock groups! If a path exists between two different clocks, then this needs to be handled by a clock domain crossing (CDC) circuit. The CDC will likely require an exception, but in almost all cases, the correct exception is NOT the set_clock_groups command. See this thread (and the threads referenced therein) on constraining clock domain crossing paths.

 

Finally to the violation itself. What you have given us doesn't really tell us much - it is a violation on userclk2. We don't know what frequency it is running at (probably 125MHz or 250MHz, but we don't know which), and we know nothing about the path itself. Is it entirely in the PCIe core? Is it in your user logic? Is it failing due to too much logic? Routing? Setup time? Hold time? Is there a few really large violations, or lots of really small violations?

 

If you want any other help on this you will have to show us a complete detailed timing report of (at least) the worst failing path...

 

Avrum

pulsar
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Registered: ‎04-16-2015

Hello avrumw

 

thank you for your quick reply.

 

>So, first, don't confuse the net name with the clock name.
>The net coming out of the PCIe block may be called user_clk, but there is nothing that says the
>clock is named user_clk - in fact, it is most probably called usrclk2.
>If you want to be sure, you can (with the synthesized or implemented design open) use the Tcl command
> get_clocks -of_objects [get_nets usr_clk]

  I did it.
get_clocks -of_objects [get_nets user_clk]
get_clocks: Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 11142.496 ; gain = 54.457 ; free physical = 24582 ; free virtual = 29828
userclk2

 

 

>If you want any other help on this you will have to show us a complete detailed timing report of (at least) the worst failing path...
As I think this information exist in the my post "PCIe design failled" on the thread PCI Express.
If it is not convenient I'll make new more compact text.

 

Best regards,
Viktor

 

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vemulad
Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Hi @pulsar

 

You can open synthesized design and generate clock interaction report from tools--> report --> report clock interaction. 

 

This would give you a table with all clock interactions. You can select cross clock domain, right click and set them as "asynchronous", this would declare those two clock domains as async. If you save the design after this, the constraint will be saved to top level xdc. 

Thanks,
Deepika.
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pulsar
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Registered: ‎04-16-2015

Re: Constraints_difficulty

 
 

Hello Deepika

 

I did

get_clocks -of_objects [get_nets user_clk]
userclk2
 

get_clocks -of_objects [get_nets user_CLK]
CLKOUT1

 

Then I  did   tools--> report --> -Timing -> Report Clock Interaction

and  found cross clock domain between  userclk2  and CLKOUT1

(blue, i.e. "User Ignored Path")

 

 

But I did not find  "asynchronous" option for them.

There are only such options:

Set Clock Group

Set False Path

Set Multicycle Path

Set Maximum Delay

 

Please advice,

 

Thank you, 

 

Best regards,
Viktor

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avrumw
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Registered: ‎01-23-2009

But I did not find  "asynchronous" option for them.

 

The "Set Clock Group" makes them asynchronous. But please re-read my original reply - it is almost never correct or safe to simply declare clocks as asynchronous. In the best of cases, you can only do so after careful analysis of all the paths between the domains.

 

Avrum

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pulsar
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Registered: ‎04-16-2015

Hello Avrum

 

You was right.

It was a simple problem within one clock - userclk2

After adding one register between  BRAM's output and PCIexpress register

Implementation works  without critical warning. 

All user specified timing constraints are met.

 

Thank you very much.

 

Best regards,
Viktor

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leif@rdos.net
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Registered: ‎12-29-2019

I'm having exactly this problem when I try to connect the 7-series PCIe to the DAQ2 card. The problem is that Vivado will assume that all clocks are synchronous, but when you do CDCs between the PCIe userclk2 and any other clock domain, this will result in timing errors and seemingly unrelated clocks that interact. The problem is to find the name of the userclk2. Userclk2 is derived internally from the pci reference clock with an MMCM, and the contraints files of the PCIe IP are hidden. It's reported with various names like userclk2, txoutclk_x0_y0. I finally succeeded by selecting report -> clock interactions and then defining these are asynchronous which will give you a very long name that can be used to create constraints ([get_clocks -of_objects [get_pins pci_app_inst/pcie_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT3]])

I've also tried to constraint only the top-level PCIe reference clock, but apparently this will not work as the generated clocks will still be believed to be synchronous.

 

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