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Explorer
Explorer
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Registered: ‎06-08-2017

Could failing timing constraints make design fail in hardware (sometimes but not always)

To give the question context: I have a design for a Kintex-7 FPGA that is basically [ADC inputs] -- [IIR filters] -- [DAC outputs]. I have never used timing constraints, partly because I didn't know how, but mostly because the design often works. I say often because sometimes I will change one part of the design and it will affect another, completely unrelated part.

 

For example, the design might be:

input0 -- filter0 -- output0.

 

And then I change to:

input0 -- filter0 -- output0

input1 -- filter1 -- output1.

Where the inputs, outputs, and filters are not connected in any way (in my verilog code), but filter0 will stop working.

 

Could this be caused by timing failure? Why would missing timing constraints cause multipliers to stop working correctly? I know my filter modules work (have checked transfer functions for many parameter ranges), and my ADC and DAC driving firmware works. But when I put everything together, sometimes things don't work.

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Mentor
Mentor
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Registered: ‎02-24-2014

Re: Could failing timing constraints make design fail in hardware (sometimes but not always)

This is a job for THE CONSTRAINTS WIZARD!

 

constraint_wiz.png

 

First load your synthesized design into Vivado  ( "Open Synthesized Design" ), and then run the constraints wizard.   This should help you get things straightened out.

 

Don't forget to close a thread when possible by accepting a post as a solution.
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Registered: ‎06-08-2017

Re: Could failing timing constraints make design fail in hardware (sometimes but not always)

I have used it actually. It correctly identifies my main (100MHz) input clock. I do not know what to put for jitter.

 

For the generated clocks section, it identifies a few clocks (I have a 10 MHz, 5 MHz, and 100kHz) but it also asks for constraints on a bunch of data lines. I do not know what to do for these. Also when I add the constraints for those clocks I get this timing report:Timing.PNG

Looks like something went wrong with that 100kHz clock if I had to guess.

 

The it has the section for input an output delays. I am not sure why I should put those constraints since I already deal with the ADC delay with IDELAYE2. Maybe it would be useful for the DACs since there is no ODELAY in those IO banks.

 

Again, I am particularly interested in if this is actually my problem. Could failing timing make DSP functions like multiplication fail to execute properly?

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Mentor
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Registered: ‎02-24-2014

Re: Could failing timing constraints make design fail in hardware (sometimes but not always)

If your main clock is 100 MHz, then this is unlikely to be a problem, unless of course,  you have zero pipelining in the DSP48 elements.   You might want to check this.   But it seems likely that you may have clock domain crossing problems,  transferring data safely from one clock domain to another.    You should be using the XPM_CDC_XXXX macros for this, since they include their own timing constraints.   

 

Try running the report for Clock Interactions...      "Reports" =>  "Timing" => "Report Clock Interaction".

 

If you see a lot of red on this diagram, then you might want to start inserting some XPM_CDC macros.

Don't forget to close a thread when possible by accepting a post as a solution.
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Explorer
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Registered: ‎06-08-2017

Re: Could failing timing constraints make design fail in hardware (sometimes but not always)

All my multipliers are inferred, not instantiated directly. So my verilog code has stuff like:

y = b*x.

 

How can I check the pipelining of the multipliers? Do I have to change my code to manually instantiate each multiplier?

 

I'll post the results of the timing report shortly. 

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