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Creating very slow clocks

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Visitor
Posts: 7
Registered: ‎04-24-2017

Creating very slow clocks

Hello,

 

I'm trying to build a system that uses very slow clocks (few of them, speeds ~10 kHz), which can't be synthesized using Xilinx's Clocking wizard IP, because that uses PLL's or MMCM's that can't  go that slow. So, I made my own counter and am using it to create clocks, from much faster system clock.

 

So, I know I could constrain those in .XDC file using "create_clock" TCL command, but the problem is that I want to connect those clocks to some AXI-Stream FIFO's and Vivado won't let me do it, because it doesn't see those signals as valid clocks, and I can't run TCL because I don't have any elaborated design opened.

 

Can you tell me how to let Vivado know I want to create clock from output pin of some module/IP?

 

Thank you

Posts: 185
Topics: 1
Kudos: 44
Solutions: 18
Registered: ‎04-18-2011

Re: Creating very slow clocks

I think you are facing more than one problem here.
You most should create a generated clock but using the fast clock as a master. This would ensure the paths can be analysed but I think you have a more serious concern. The axi stream is likely to be supported in a given frequency range, I doubt it is intended to run this slow.
Also it's worth pointing out that the output of a flip flop needs to route from general routing and find it's way onto the global clock tree via a bufg which is not always ideal in FPGA
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Xilinx Employee
Posts: 328
Registered: ‎07-30-2007

Re: Creating very slow clocks

It might be better to use a faster clock out of a PLL and use the counters to enable your logic at the desired intervals.  Hard to say without knowing more about your design.

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Visitor
Posts: 7
Registered: ‎04-24-2017

Re: Creating very slow clocks

[ Edited ]

Hi, and thank you both for your replies.

 

As I said, I can't use PLL, because I want to create 48 kHz clock signal from 24 MHz clock. Now, I know I can use counter to slow this down, but when I try to connect this output pin (from counter module) to clk pin of axi stream data fifo, I get a warning saying pin types don't match. As I said, usually I would constrain this path (and put it trough BUFG), using "create_clock", but I'm still unable to do this. 

Now, you said something about BUFGs not being ideal in FPGA, besides possible timing problems, is there anything else I should worry about?

 

Also, I'm not sure about allowed freq range on Axi Stream interface, I've never seen anything on that topic, and I didn't think it existed because its a pretty simple protocol, that also does some handshaking. Is there some range, and, if it is, can you please provide some info?

Instructor
Posts: 3,874
Registered: ‎01-23-2009

Re: Creating very slow clocks

There is probably no minimum frequency on an AXI stream. However even 24MHz is very slow in an FPGA - at this frequency you can do pretty much anything you would reasonably need to do in a single clock. Therefore generating (and using) an even slower clock will not likely make a difference in terms of optimization (utilization, timing closure).

 

So rather than try and create and us a 48kHz clock, why not just run on the 24MHz clock with a non-continuous AXI stream. All AXI stream masters have an "VALID" signal - this is a signal you can assert and deassert as necessary to signal valid data from the master. If the master only has valid data 48,000 times a second, then you can simply assert this signal with each new valid data - in essence once out of every 500 clocks. Done this way, you have only one clock (the 24MHz one) and the data rate matches what you need - 48000 data per second.

 

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