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Visitor john9636
Visitor
280 Views
Registered: ‎04-08-2019

DSP48E1 Time Multiplex

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Hi,

According to the UG479 (7 Series DSP48E1 Slice User Guide), the DSP slices in 7 seires FPGA is recommended to be used in time multiplex mode. I am trying to use this mode.  But I find it difficult to raise the clock frequency, because the delay of the net between two clock domain is high.

The extreme frequency of DSP slices is about 650 MHz in the FPGA (XC7K325T FFG900-2)  on the KC705 evaluation board. So I wanna set the system clk frequency as 300 MHz, and the dsp clk frequency as 600 MHz. I use two cascaded registers in two clock domain which transfer the input data to the DSP slices to solve the problem of spanning clock domain. And I just use two constraint instructions to constraint the two clock:

create_clock -name clk -period 4.000 [get_ports clk]
create_clock -name dsp_clk -period 2.000 [get_ports dsp_clk]

But I find the maximum clk frequency is only about 500 MHz, and the key path is always between the two clock domain. What should I do about this?

 

Thank you.

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1 Solution

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Historian
Historian
189 Views
Registered: ‎01-23-2009

Re: DSP48E1 Time Multiplex

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Let's take a step back...

Where are these two clocks coming from? How do you have two different clocks at different pins of your FPGA that are exactly synchronous and phase aligned? Because this is what you are informing the tools by the constraints and structure you have in place. This is very unlikely.

Furthermore, as you are seeing, even if you did have this "unusual" clock input situation, you would not be able to move data between these two domains synchronously. Your clock paths skew is large (352ps) and negative, meaning that this path had a significant hold time violation that the tool had to (at least try to) fix - it may have succeeded. But regardless, by trying to fix this large hold time violation (by adding extra delay - clearly visibly through the fact that there is 1.166ns of routing delay between these two flip-flops) this violated the setup time on this path. Routing delay is highly process/voltage/temperature dependent; so adding 350ps of delay at min delay would add more than 1ns of delay at max delay (roughly 3:1 ratio) - which is the violation you are seeing here.

To attempt what you are considering, you need your two clocks to be much more closely skew aligned. To start with, they cannot both come from external pins; even if you have a proper clock divider outside the FPGA, this is unlikely to work.

To get these two clocks, you need to have them come from the same MMCM or PLL. Bring in one of the clocks and route it to the MMCM/PLL. Program the MMCM/PLL to generate the two clocks you need - the 1x and 2x clocks (so, if you bring in the slower clock, have one output do x1 and the other do x2). Route both of these two a BUFG. If you are using UltraScale/UtraScale+ then you need to place the two clock nets in the same CLOCK_DELAY_GROUP (this doesn't apply for 7 series).

With this topology, you should be able to transfer data synchronously between the two domains - a 1.668ns path should be doable.

Avrum

6 Replies
Xilinx Employee
Xilinx Employee
269 Views
Registered: ‎05-14-2008

Re: DSP48E1 Time Multiplex

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It looks to me that your timing problem has nothing to do with the time multiplex mode of DSP, but just CDC paths from 300MHz to 600MHz directly. Am I correct?

Can you attach your timing report or screenshots of the timing violation you have?

-vivian

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Visitor john9636
Visitor
245 Views
Registered: ‎04-08-2019

Re: DSP48E1 Time Multiplex

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Yes, I think so. 

I usually solve the span clock domains problem with FIFO formed with Distributed RAM or BRAM. But this time, I have to use a few registers. 

The timing report is attached.

Thank you very much.

Moreover, here I just constraint a module with two clock domains. I tried that if I used PLL to get the dsp clk in the top module, whose frequency was double frequency of the system clk, the timing report was worse. So maybe I am not solving this problem in a correct way.

批注 2019-09-17 141332.jpg

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Moderator
Moderator
219 Views
Registered: ‎01-16-2013

Re: DSP48E1 Time Multiplex

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Hi @john9636 

Please share your timing report (The file name ends with *.rpt) the snapshot you have shared will not help much to identify the issue/root cause.

Thanks,
Yash

 

Visitor john9636
Visitor
203 Views
Registered: ‎04-08-2019

Re: DSP48E1 Time Multiplex

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Got it. Here are some screenshots of a typicle key path. 

1.jpg2.jpg3.jpg

Should I do something suggested by the advice - "Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path."?

Thank you very much.

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Historian
Historian
190 Views
Registered: ‎01-23-2009

Re: DSP48E1 Time Multiplex

Jump to solution

Let's take a step back...

Where are these two clocks coming from? How do you have two different clocks at different pins of your FPGA that are exactly synchronous and phase aligned? Because this is what you are informing the tools by the constraints and structure you have in place. This is very unlikely.

Furthermore, as you are seeing, even if you did have this "unusual" clock input situation, you would not be able to move data between these two domains synchronously. Your clock paths skew is large (352ps) and negative, meaning that this path had a significant hold time violation that the tool had to (at least try to) fix - it may have succeeded. But regardless, by trying to fix this large hold time violation (by adding extra delay - clearly visibly through the fact that there is 1.166ns of routing delay between these two flip-flops) this violated the setup time on this path. Routing delay is highly process/voltage/temperature dependent; so adding 350ps of delay at min delay would add more than 1ns of delay at max delay (roughly 3:1 ratio) - which is the violation you are seeing here.

To attempt what you are considering, you need your two clocks to be much more closely skew aligned. To start with, they cannot both come from external pins; even if you have a proper clock divider outside the FPGA, this is unlikely to work.

To get these two clocks, you need to have them come from the same MMCM or PLL. Bring in one of the clocks and route it to the MMCM/PLL. Program the MMCM/PLL to generate the two clocks you need - the 1x and 2x clocks (so, if you bring in the slower clock, have one output do x1 and the other do x2). Route both of these two a BUFG. If you are using UltraScale/UtraScale+ then you need to place the two clock nets in the same CLOCK_DELAY_GROUP (this doesn't apply for 7 series).

With this topology, you should be able to transfer data synchronously between the two domains - a 1.668ns path should be doable.

Avrum

Visitor john9636
Visitor
170 Views
Registered: ‎04-08-2019

Re: DSP48E1 Time Multiplex

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Got it.
Thank you so much.
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