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Dra92
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Registered: ‎08-18-2020

Define the required delay routine

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Hi every one

I want to know, how can I define the required delay routine and ISE finds the paths can meet my defined delay?

I want to find some routes that generate pre-defined values of delay in my circuit.

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drjohnsmith
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Registered: ‎07-09-2009

I have not manually placed in ISE for a good few decades,

   there are plenty of references on line

e.g. https://www.xilinx.com/support/documentation/sw_manuals/help/iseguide/mergedProjects/fpga_editor/html/fe_df_placing_and_routing_critical_components.htm

 

A good place to start would be a search on how to create an oscillator in an FPGA 

    the problems they have are the same as you will find,

    how to disable circuit optimisatoin, how to constrain and lock parts in place

   something like this 

https://forums.xilinx.com/t5/Other-FPGA-Architecture/How-to-implement-a-ring-oscillator-with-routings-of-FPGA-Where/td-p/768444

 

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drjohnsmith
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Registered: ‎07-09-2009

I think you are looking in the wrong direction,

There is no way in FPGAs to define a set delay to be achieved in a path,

    the tools expect a maximum delay parameter and work to get under that 

 

We have over the years , many people making oscillators on FPGAs,

     prinmeraly for Crypto designs

 

If you could give us some insight as to what your wanting to make, then we might be able to help.

 

 

 

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Dra92
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Registered: ‎08-18-2020

Thank you for this response.

I want to define a delay period, then ISE finds several different paths that can meet this conditional. 

If there is a way to define these paths manually, it is also an acceptable way. I want to use wire are outside of SLICEs in my circuit. Find the delay of each of them approximately, consequently use them.

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richardhead
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Registered: ‎08-01-2012

Are you trying to define a minimum routing delay, or maximum routing delay?

Max routing delay would be defined automatically when you set a clock period. Specifying a minimum routing delay internally is basically not possible. Having any design with a required delay internally is likely not going to work or not be a sensible solution.

drjohnsmith
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Registered: ‎07-09-2009

Sorry @Dra92 , thats not the way the tools work,

In FPGA designs we are interested in max delays, which specify how fast the circuit can work,

    and the tools take care of ensuring set up / hold times are meet .

FPGAs are basically a synchronous device, running off clocks.

 

You can place by hand individual "units" such a CLB's within the FPGA 

    its done by those wanting to try to make oscillators out of gates 

BUT , you have to understand the timing system in the FPGA.

    FPGAs speed varies depending upon Process, Voltage and temperature,

        Also different parts of the chip can be slightly faster than others,

       so even if you manage to measure the delay through one "unit" on one FPGA, The next FPGA it will be a different delay.

All of the PVT and placement variations are taken care of by the tools, when we specify the period ( frequency ) we want the circuit clocks to run at,

 

   

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Dra92
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Registered: ‎08-18-2020

Thank you for the comprehensive response; I got what you mean.
Is there any way to manually define paths from one point to the other point? Of course, they must be out of SLICEs, and between the CLBs? Then I find the max delay of these several paths as you told me.
PS: I mean from "manually" is such as when we use the primitives in SLICE.

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drjohnsmith
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Registered: ‎07-09-2009

I have not manually placed in ISE for a good few decades,

   there are plenty of references on line

e.g. https://www.xilinx.com/support/documentation/sw_manuals/help/iseguide/mergedProjects/fpga_editor/html/fe_df_placing_and_routing_critical_components.htm

 

A good place to start would be a search on how to create an oscillator in an FPGA 

    the problems they have are the same as you will find,

    how to disable circuit optimisatoin, how to constrain and lock parts in place

   something like this 

https://forums.xilinx.com/t5/Other-FPGA-Architecture/How-to-implement-a-ring-oscillator-with-routings-of-FPGA-Where/td-p/768444

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Dra92
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Registered: ‎08-18-2020

1.JPG

2.JPG

  I followed the instruction that you gave me. There is one problem; the manually option is disable. Do you know the reason ?

I want to find several different paths between a carry-chain and a flip flop. 

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drjohnsmith
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Registered: ‎07-09-2009

No is easy answer

What is your aim here ?

 

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Dra92
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Registered: ‎08-18-2020

I want to define two or more paths between carry-chain and flip-flop with a different maximum delay of routing. The primary variable of this design must be the routing delay in different paths. By changing each path, I want to change the delay between these two ones.

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drjohnsmith
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Registered: ‎07-09-2009

Some sort of random number generator.

Sorry, the tools are not designed to take an absolute timing to be meet , but a maximum they must get under.

  how far under that time is not possible to define.

 

If you do find a way,

 

please come back to the forums with your answer .

 

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Dra92
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Registered: ‎08-18-2020
Thanks for your help