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Contributor
Contributor
3,230 Views
Registered: ‎09-24-2016

Delays reported by Vivado

Hi,

 

Given a net NetAB linking an output of LUTA to an input of LUTB. When increasing the fanout, i.e the output of LUTA is also linked to an input of another LUTC, i found that the delay of NetAB has increased by the same amount in the Max slow, Min slow, Max fast and Min fast process corners. Is it normal? I was expecting that the delay increase is the highest in the Max Slow and the lowest in the Min fast process. does anyone have an explanation?

 

Thank you for your help,

 

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Contributor
Contributor
3,091 Views
Registered: ‎09-24-2016

Based on my knowledge, increasing the fanout adds wire segments and pips (pass transistor) to the net. If modeled as an RC distributed network with (LUT) driving strengths that depend on corner cases, the delay increase should also depend on corner cases.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

Can you show us an example?

 

Thanks

Vivian

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Contributor
Contributor
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Registered: ‎09-24-2016

According to Vivado Timing analyzer, The delay of the net plotted in red color in Fig.1 is equal to:

472 ps in Slow Max

314 ps in Slow Min

265 ps in Fast Max

190 ps in Fast Min 

 

When the fanout is increased as Shown in Fig.2, the delay of the same net (red) is now equal to:

479 ps in Slow Max

321 ps in Slow Min

272 ps in Fast Max

197 ps in Fast Min 

 

So the delay increase is equal to 7 ps in all process corners. Do you have any explanation? I expected that the delay increase should be the highest in the Slow process corner and the lowest in the Fast process corner.

Fig.1.PNG
Fig.2.PNG
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