08-23-2020 12:34 AM
I am working on a vivado project in which I have Xilinx's IPs and also some of my HLS generated IPs and has ILA to observe the results. When I go for simulations , design produces desired result but when it comes to run on board it does not produce the same result. Here what I've observed in ILA is that before the desired data some garbage data comes on the data bus and I do not have any idea why is it happening.
Any suggestions would be very helpful.
08-23-2020 05:38 AM
08-27-2020 02:24 AM
What do those garbage data look like?
Can you paste a screenshot of the ILA waveform?
08-31-2020 05:16 AM
Right now I do not have snapshot of ILA but I will share it with you but till then I can tell you that by garbage I meant to say undesired data.
Let's say we have 128 bit bus then in the starting for 3 or 4 buses thar undesired data appears and only after that the desired data comes on the bus of 128 bits.