Hello, I'm new to using FPGAs. I currently have the ISE 10.1 suite installed including System Generator, as well as the full Matlab/Simulink Suite. I'm trying to build a simple design for a Spartan3A DSP fpga. I have used an example with my Board Support Package from the board supplier (Innovative Integration X3-25M) and that works properly with the JTAG and I can run a co-sim. Now, when I try to design my own system, I run into problems with Xflow and latency issues.
Basically, I'm trying to figure out what the latency per block is. For instance, in one example I have, a DSP48 block has a latency of 5. If that wasn't in the example, I wouldn't know how to figure that out. Is there any way that you can verify what latency you need so you can properly add your delays lines?
I have tried the "format->block display-> execution order contect indicator" in Simulink but that does not appear to work with the Xilinx blocks.