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antda
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Registered: ‎03-07-2013

Different results in console and in static timing report

Dear all,

 

I have noted that my project implemented (PAR) on Virtex-6 XC6VLX195T gives different results about the minimum clock period in console and in post-PAR static timing report.

 

In particular, this is what printed in console during the PAR process:

"

----------------------------------------------------------------------------------------------------------
  Constraint                                                                   |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                                                                       |                    |    Slack         | Achievable | Errors   |    Score   
----------------------------------------------------------------------------------------------------------
* TS_clk = PERIOD TIMEGRP "clk" 11 ns HIGH  | SETUP      |    -0.113ns   |    11.113ns |       7     |         398
  50%                                                                              | HOLD       |     0.021ns    |                      |       0     |           0
----------------------------------------------------------------------------------------------------------

"

 

and this is what written in post-PAR static timing report:

"

Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 12 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 583051728 paths analyzed, 172168 endpoints analyzed, 2387 failing endpoints
 2387 timing errors detected. (2383 setup errors, 4 hold errors, 0 component switching limit errors)
 Minimum period is  13.918ns.

"

[...]

"

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
                          | Src:Rise  | Src:Fall    | Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall |Dest:Fall|
---------------+---------+---------+---------+---------+
clk                     |   13.178   |    6.959    |    6.686    |    5.226|
---------------+---------+---------+---------+---------+

"

 

I use ISE 14.4 on workstation Linux 64bit.

I noted that other projects do not present the same incoherence.

 

Has anyone an idea about such differences? What result should I consider as the correct one?

 

Thanks in advance,

Antonio :)

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austin
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Registered: ‎02-27-2008

a,


What is in the timing report when all is done?  What errors or warnings are there at the very end (look at all the reports, and the final lines of the log)?  How much positive slack do you have on the ten worst paths?  If there are errors, you will not be able to generate a bitstream.  Can you generate a bitstream?

 

It is only the final reports that you need to be concerned about.  The intermediate results are an indicator of just how much work it takes to place and route and meet all the constraints.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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antda
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Registered: ‎03-07-2013

Thank you Austin, your reply has been very clear.

 

Antonio

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