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Visitor tishi
Visitor
427 Views
Registered: ‎02-12-2019

Does the route path length related to net delays?

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Here are two paths, the red highlighted one from DSP48E1 instance to LUT2 instance is o[0], you can see the net delay is 0.298 from the below timing report,

net (fo=2, routed) 0.298 0.834 cabac_inst/o[0]

the yellow highlighted one is r_wire[8], you can see the net delay is 0.818 from the timing report,

net (fo=1, routed) 0.818 4.045 r_wire[8]


Seems the red path from DSP48E1 instance to LUT2 instance is much longer than the yellow path from CARRY4 to FDRE,
Why the longer one has the smaller net delay?

 

longshort3.png

 

timing1.jpgtiming2.jpg

 

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Teacher drjohnsmith
Teacher
413 Views
Registered: ‎07-09-2009

Re: Does the route path length related to net delays?

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Bottom line ,
Yes longer path is longer delay ,

BUT

a) the picture is just that, not much relationship to the real chip layout,
b) there are different route types inside the chip, with different delays per thou,

Once upon a time it used to be simple, we could actually edit routes / PIPs by hand and the tools were dumb.

Then long and short lines came in, and we could still edit routes by hand, but the tools got smarter and the complexity went up.

Now, all sorts of other types of routes have come along, and the tools / processing power is way better at spotting best routes and compromises than humans.

That looks like ISE, which is one generation removed from Vivado, but still very good.

Remember , bottom line the tools are running to meet your timing constraints, not find the fastest route . Some times that will be the fastest, others they will meet your timing and stop.

constrain the timing you need, and just believe the tools reports.

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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5 Replies
Teacher drjohnsmith
Teacher
414 Views
Registered: ‎07-09-2009

Re: Does the route path length related to net delays?

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Bottom line ,
Yes longer path is longer delay ,

BUT

a) the picture is just that, not much relationship to the real chip layout,
b) there are different route types inside the chip, with different delays per thou,

Once upon a time it used to be simple, we could actually edit routes / PIPs by hand and the tools were dumb.

Then long and short lines came in, and we could still edit routes by hand, but the tools got smarter and the complexity went up.

Now, all sorts of other types of routes have come along, and the tools / processing power is way better at spotting best routes and compromises than humans.

That looks like ISE, which is one generation removed from Vivado, but still very good.

Remember , bottom line the tools are running to meet your timing constraints, not find the fastest route . Some times that will be the fastest, others they will meet your timing and stop.

constrain the timing you need, and just believe the tools reports.

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

Visitor tishi
Visitor
389 Views
Registered: ‎02-12-2019

Re: Does the route path length related to net delays?

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That sounds frustrating we could do nothing to improving the routing, 

Sometimes I do lots of optimization of the code to reduce logic levels but then after implementation, the net delays increase, the critical path is even longer.

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Teacher drjohnsmith
Teacher
353 Views
Registered: ‎07-09-2009

Re: Does the route path length related to net delays?

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Remember the tools take your "paths" and "mash them up",
the way to minimise the delays is to add more register stages, so the amount of logic is less between registers, remember a 4 or 6 input LUT is the logic you have without routing,

Use the facilities of the device, such as the ripply carry chain,
( counters and adders are fast because of this )

Use th ebuilt in functoins of the FPGA such as BRAM and DSP blocks, just rember to allow for enough registers.

Also note , tings like the BRAMs are arranged next to the DSP blocks, so make great filters, but if you dont follow the guide, you can end up with signals having to come out of the BRAM, into some external gating then back into the DSP, adding delay.

Bottom line, for speed yo need to know your architecture of the FPGA,
this is the thing thats killing HLS,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Guide avrumw
Guide
349 Views
Registered: ‎01-23-2009

Re: Does the route path length related to net delays?

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In addition to what others have said, I think we have overlooked the most singificant reason why you are seeing these differences...

All static timing (setup and hold) is performed at two timing corners - named "Slow Process Corner" and "Fast Process Corner". The difference in delay of a given cell/interconnect is quite large between these two - usually in the ratio of 3:1.

By default, for a given path, the tool reports the worst timing result from the two timing corners. Generally (not always) a setup check is worst at slow process corner and a hold time at fast timing corner.

For your red net (the long one) we can clearly see in the report that it is at the "Fast Process Corner".

For your yellow net (the shorter one) the header is cut off, so we can't see the timing corner, but it is a setup check, so is likely at the "Slow Process Corner". If this is the case, this is the main reason that this report is showing a significantly higher delay than the other one.

If you looked at these at the same timing corner, you would probably find that the shorter net does, in fact, have less delay (or at least more similar delay - the longer net is clearly using a "long line" which is faster than several short lines).

Avrum

 

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Visitor tishi
Visitor
261 Views
Registered: ‎02-12-2019

Re: Does the route path length related to net delays?

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@avrumw thanks, things is just like what you said.
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