Extra Clock Delay in Post-Place & Route Simulation

[burak_kelleci]

Hi,

I used Spartan xc3s250-4cp132 device and ISE 12.3 Webpack edition to synthesize, place & route and simulate the following design. The design is timing closed. There is no timing violations but the post-place & route simulation shows oen extra clock delay. If I inreased the clock period from 10ns to 30ns there is no extra delay. Any idea where this extra clock delay comes from?

Design:

Library ieee;
use ieee.std_logic_1164.ALL;

ENTITY BeltWarn IS
 PORT(k,p,s: IN std_logic;
   w: OUT std_logic );
END BeltWarn;

ARCHITECTURE Behav OF BeltWarn IS
SIGNAL w_temp: std_logic;
BEGIN
 PROCESS(k,p,s)
 BEGIN
  IF(k = '1' AND k'EVENT) THEN
   w_temp <= (p AND NOT(s));
  END IF;
 END PROCESS;
 w <= w_temp;
END Behav;

TestBench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY Testbench IS
END Testbench;

ARCHITECTURE TBarch OF Testbench IS
 COMPONENT BeltWarn IS
  PORT(k,p,s: IN std_logic;
    w: OUT std_logic);
 END COMPONENT;

 SIGNAL k_s, p_s, s_s, w_s: std_logic;
 
 BEGIN
  CompToTest: BeltWarn
   PORT MAP(k_s, p_s, s_s, w_s);

  PROCESS
  BEGIN
   p_s <='0'; s_s<='0';
   WAIT FOR 42 ns;
   p_s <='0'; s_s<='1';
   WAIT FOR 40 ns;
   p_s <='1'; s_s<='0';
   WAIT FOR 40 ns;
   p_s <='1'; s_s<='1';
   WAIT FOR 40 ns;
   p_s <='0'; s_s<='1';
   WAIT FOR 40 ns;
   p_s <='0'; s_s<='0';
   WAIT;
  END PROCESS;
  
  PROCESS
  BEGIN
   k_s <= '1';
   WAIT FOR 5 ns;
   k_s <= '0';
   WAIT FOR 5 ns;
  END PROCESS;
END TBarch;

UCF file:

NET "k" TNM_NET = k;
TIMESPEC "TS_k" = PERIOD "k" 10 ns HIGH 50%;
NET "p" OFFSET = IN 2 ns VALID 5 ns BEFORE "k" RISING;
NET "w" SLEW = FAST;
NET "s" OFFSET = IN 2 ns VALID 5 ns BEFORE "k" RISING;
NET "w" OFFSET = OUT 6 ns AFTER "k" REFERENCE_PIN "w" RISING;
INST "w_temp" IOB=TRUE;

[gszakacs]

It looks to me like your testbench is violating the timing you specify in the constraints.  The

constraint:

NET "p" OFFSET = IN 2 ns VALID 5 ns BEFORE "k" RISING;

means that signal "p" should have at least 2 ns of setup and 3 ns of hold time

with respect to the rising edge of "k".  However your main process only provides

2 ns of hold time with respect to "k".  Strangely though I don't see how that would

create an extra clock delay, I would think it would more likely create one less

clock if the hold time requirement exceeded 2 ns.  Can you post a waveform

from the post P&R simulation to show where you see the extra delay?

[burak_kelleci]

Hi,

Thanks for your reply.

 I also tried with 4ns hold time. But the result is still the same. I added my simulation results, including the internal signals at the register inputs and output. Around 100ns the DFF requires two clock cycles in order to sample right value. Below is the timing analysis results.

 All constraints were met. 

 Data Sheet report: 

 ----------------- 

 All values displayed in nanoseconds (ns) 

 Setup/Hold to clock k 

 ------------+------------+------------+------------------+--------+ 

             |Max Setup to|Max Hold to |                  | Clock  | 

 Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  | 

 ------------+------------+------------+------------------+--------+ 

 p           |    0.576(R)|    0.743(R)|k_BUFGP           |   0.000| 

 s           |    0.261(R)|    1.172(R)|k_BUFGP           |   0.000| 

 ------------+------------+------------+------------------+--------+ 

 Clock k to Pad 

 ------------+------------+------------------+--------+ 

             | clk (edge) |                  | Clock  | 

 Destination |   to PAD   |Internal Clock(s) | Phase  | 

 ------------+------------+------------------+--------+ 

 w           |    5.396(R)|k_BUFGP           |   0.000| 

 ------------+------------+------------------+--------+ 

 COMP "p" OFFSET = IN 2 ns VALID 5 ns BEFORE COMP "k" "RISING"; 

 Worst Case Data Window 1.319; Ideal Clock Offset To Actual Clock 0.417;  

 ------------------+------------+------------+---------+---------+-------------+ 

                   |            |            |  Setup  |  Hold   |Source Offset| 

 Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  | 

 ------------------+------------+------------+---------+---------+-------------+ 

 p                 |    0.576(R)|    0.743(R)|    1.424|    2.257|       -0.417| 

 ------------------+------------+------------+---------+---------+-------------+ 

 Worst Case Summary|       0.576|       0.743|    1.424|    2.257|             | 

 ------------------+------------+------------+---------+---------+-------------+ 

 COMP "s" OFFSET = IN 2 ns VALID 5 ns BEFORE COMP "k" "RISING"; 

 Worst Case Data Window 1.433; Ideal Clock Offset To Actual Clock 0.044;  

 ------------------+------------+------------+---------+---------+-------------+ 

                   |            |            |  Setup  |  Hold   |Source Offset| 

 Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  | 

 ------------------+------------+------------+---------+---------+-------------+ 

 s                 |    0.261(R)|    1.172(R)|    1.739|    1.828|       -0.044| 

 ------------------+------------+------------+---------+---------+-------------+ 

 Worst Case Summary|       0.261|       1.172|    1.739|    1.828|             | 

 ------------------+------------+------------+---------+---------+-------------+ 

 COMP "w" OFFSET = OUT 6 ns AFTER COMP "k" REFERENCE_PIN BEL "w" "RISING"; 

 Bus Skew: 0.000 ns;  

 -----------------------------------------------+-------------+--------------+ 

 PAD                                            | Delay (ns)  |Edge Skew (ns)| 

 -----------------------------------------------+-------------+--------------+ 

 w                                              |        5.396|         0.000| 

 -----------------------------------------------+-------------+--------------+ 

 Timing summary: 

 --------------- 

 Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0) 

 Constraints cover 3 paths, 0 nets, and 4 connections 

 Design statistics: 

    Minimum period:   3.160ns{1}   (Maximum frequency: 316.456MHz) 

    Minimum input required time before clock:   0.576ns 

    Minimum output required time after clock:   5.396ns 

 ------------------------------------Footnotes----------------------------------- 

 1)  The minimum period statistic assumes all single cycle delays. 

[gszakacs · Accepted solution]

I think you may be running into a simulation issue with global set/reset.  I'm not

sure if the same thing happens in VHDL simulation, but at least for Verilog there

is an automatically generated GSR signal that holds any library model in its

initial state for the first 100 ns of simulation.  So what you see here may be

related to this issue.  Try delaying your initial stilmulus for 100 ns and see if

the W output follows P and S by a single clock cycle then.

Regards,

Gabor

[burak_kelleci]

Hi,

You are right, When I wait 100ns, the results are as expected. Thanks for the solution. I attached the results with 100ns wait included.