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Registered: ‎07-10-2019

FPGA mips frame CPU

Hello, we are new to FPGA, use mips to make a cpu architecture, form instructions, write programs in assembly language to complete functions, vivado function simulation is successful, but timing simulation, the input instructions change from 32 bits to 30 bits, and High impedance is present, please ask the reason and solution.

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Registered: ‎06-21-2017

Re: FPGA mips frame CPU

Look in your synthesis and implimentaion reports.  Did any of the instr signals get trimmed?  If so, the simulator cannot show them.

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