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jrdev
Visitor
Visitor
210 Views
Registered: ‎03-17-2021

Failed timing

Hi All,

I'm trying to use a  Spartan 7 as a RGMII passthrough (125MHz clock). The FPGA is connected between a MAC and a  PHY.

I've read many posts in this forum regarding this issue , but I still can't figure out what I'm doing wrong in the TX path...

RX clock and data are entering the FPGA as edge aligned DDR and the TX clock and data are entering the FPGA as centered aligned DDR. I assume that clock and data are perfectly aligned so after using the Vivado template for input delay constraints i get 4 ns as the max delay and 0 ns for the min delay (for both pos and neg edges).
Both Rx and TX clocks are going through BUFIO and entering to the DDR data flops. The clocks are forwarded out using an ODDR with D1,D2 pulled high and low. 

I'm using IDDR/ODDR for all data ports, and data is captured using the clock I/O port which drives a BUFIO.

My constraints for the TX path are:

create_clock -period 8.000 -name I_CLK -waveform {0.000 4.000} [get_ports I_CLK]
create_generated_clock -name txclk_bufio -multiply_by 1 -source [get_ports I_CLK] [get_pins txclk_bufio/O]

set input_tx_ports [list TXD0 TXD1 TXD2 TXD3 TXEN];

set_input_delay -clock I_CLK -max 4 [get_ports $input_tx_ports];
set_input_delay -clock I_CLK -min 0 [get_ports $input_tx_ports];
set_input_delay -clock I_CLK -max 4 [get_ports $input_tx_ports] -clock_fall -add_delay;
set_input_delay -clock I_CLK -min 0 [get_ports $input_tx_ports] -clock_fall -add_delay;

*I_CLK is the input clock port.

Still timing is failing: Worst Hold Slack is -2.598 ns.

Changing the main clock's (I_CLK) waveform to {2 6} also didn't help.
Are my constraints ok? what am I doing wrong?

Thanks in advance!

 

 

 

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viviany
Xilinx Employee
Xilinx Employee
158 Views
Registered: ‎05-14-2008

Do you have the Datasheet of the device that provides the RX clock and data for FPGA?

In the Datasheet you can find the timing diagram and timing characteristics of the clock and data. 

Use these information to create the input delay constraints.

-vivian

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