cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
marrud
Visitor
Visitor
340 Views
Registered: ‎03-12-2021

Finding the actual input and output delay constraints for my design

Greetings,

I am analysing a SPI master design in Vivado to analyse how different operating frequencies affects the power consumption. In order to have as large accuracy as possible for the power analysis/report, Vivado tells me to fill out various timing constraints for the design. I have looked into various guides and forums so I know the procedure to set the values, but as I am new to FPGA design I struggle to find out what these values actually should be.

I am using the Timing constraint wizard and has set the different clocks using create_clock, but when I get to Input/Output delays I have to set different delay parameters for different signals. The datasheet for the design only presents a maximum operating frequency, so I wondered if anyone know if it is possible to do some analysis to find the required delay parameter or how this should be done?

Looking forward to an answer

Best regards

Markus

4 Replies
maps-mpls
Mentor
Mentor
273 Views
Registered: ‎06-20-2017

The set_input_delay and set_output_delay are to specify aspects of your design that Vivado cannot possibly know.  Specifically, Vivado doesn't know external flight delays on data and clock, or the trace lengths, or the setup,hold requirements of downstream synchronous devices, or the clock to out min/max of upstream devices.  You get this data from the datasheets of the upstream/downstream devices, and the board delays and trace lengths from your board designer (or you get the board design files and compute it yourself). 

*** Destination: Rapid design and development cycles ***
0 Kudos
marrud
Visitor
Visitor
214 Views
Registered: ‎03-12-2021

Greetings,

thank you very much for the reply, but I have some followup questions. I am only looking into the design of a SPI master and the upstream device is therefore unknown (Just to be sure; by upstream/downstream devices it is meat the devices my design is connected to, for instance a CPU as the upstream device and a SPI slave as the downstream device, or is that wrong?). The only thing my design is connected to is the testbench for simulation purposes. I have attached the waveforms from the constraints wizard. As seen in the input delay waveforms I need to fill in data for trco_min, trce_dly_min, tfco_min ++. Since I don't have a specified upstream device, does this means that it is impossible for me to fill in these values? If so, do you happen to know an example of such a device so I can look into it av extract the delays from there? I also wonder about the same for the downstream devices since I have looked into the datasheets of different SPI slaves, but can't find some reasonable values for these constraints. 

Also for the board trace delay, is this something normally found in the datasheets for the FPGA? I have tried to look into the datasheets of the board, but struggle to understand where to find it, if it exists there or what to look for. I use the Zynq-7000 product family with part xc7z020clg400-1 if that might help. I also tried to export the I/O-ports to a csv-file using file->export->export I/O-ports. In this csv-file I get some values for Min Trace Delay (ps) and Max Trace Delay (ps). Is these the values I should use for the board trace delay?

This is my first design with using constraints, so I would be grateful for any tips. I have looked into multiple user guides, tutorials and forums, but I only find guides on how to set constraints in Vivado, and not how to actually find the values on the constraints.

I hope you are able to give some more tips

Best regards

Markus

OutputDelay2.png
InputDelay2.png
Outputdelay.png
InputDelay.png
0 Kudos
maps-mpls
Mentor
Mentor
188 Views
Registered: ‎06-20-2017

Regarding board delays, "the board delays and trace lengths from your board designer (or you get the board design files and compute it yourself). "

Regarding SPI, look to see if there is a standard, and if not, look at data sheets.   If I remember correctly, typically for slower interfaces like this, the tsu and thd are so much smaller than the clock period that you typically drive data on one clock edge, and sample it on the other.  In which case, unless you have really really really long board delays (or a long cable you're attempting to work across) you will probably be good if you look through a bunch of data sheets, and double the maximum setup and double the maximum hold, and double the maximum clock to out.

If you work for a company, I'd recommend FPGA-STAXDCADV training.  It is a 3-day advanced training, and fast paced.  You cannot capture it here.

If you're on your own or a student, I'd recommend you keep reading and thinking and asking questions.  Unfortunately, I don't have the time to teach you more beyond what I have here, but others might. 

Here are some links:

https://www.xilinx.com/video/hardware/design-constraints-overview.html

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug945-vivado-using-constraints-tutorial.pdf

https://www.xilinx.com/video/hardware/using-vivado-timing-constraint-wizard.html

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug906-vivado-design-analysis.pdf

 

*** Destination: Rapid design and development cycles ***
marrud
Visitor
Visitor
155 Views
Registered: ‎03-12-2021

Thanks again for the reply, I looked into the link you provided, and they gave som more knowledge about the constraints. I will then look furter into what the actual numbers should be and see if I find something useful. If anyone happen to know some typical numbers for the SPI interface, I would be very grateful.

I am still a student so I stay with the reading for now, but hanks for the tips so far!

Best regards

Markus

0 Kudos