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1,307 Views
Registered: ‎12-30-2018

Getting Critical Warning “[Timing 38-282] The design failed to meet the timing requirements.”When tried to achieve output frequency of 930Mhz from clocking wizard IPcore using diff. input 200Mhz

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I am trying to achieve max. clock frequency from clocking wizard(i.e 933Mhz) using differential input of 200Mhz  without critical warning.I have achieved 933 MHz but with critical warning “[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations”. Getting this warning when I increases the frequency more than 714 Mhz.

There is an issue of negative slack but I am not able to solve the issue.How can I solve this issue?

Project and warning screenshot is attached.  

Thanks in advance

Regards,

Mufasir Fida Qureshi

print_screen_warning.png
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1 Solution

Accepted Solutions
Historian
Historian
1,160 Views
Registered: ‎01-23-2009

Re: Getting Critical Warning “[Timing 38-282] The design failed to meet the timing requirements.”When tried to achieve output frequency of 930Mhz from clocking wizard IPcore using diff. input 200Mhz

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First, in order to ensure that you are not using a BUFG, in the "Clocking Options" tab, you must deselect "Phase Alignment" - using "Phase Alignment" uses a BUFG between CLKFBOUT and CLKFBIN - turning it off uses the internal feedback path which doesn't limit the design to the frequency of the BUFG.

Then, once the clock is generated, it cannot use any clock buffer (since all the clock buffers have maximum frequencies less than 933). So, I repeat the question - what do you want to do with this? As I said, a clock of this speed is unusable inside the FPGA - none of the resources will run this fast. Are you simply trying to generate a clock going out of the FPGA at this speed? If so, it is unclear what you are going to get. Very few of the I/O standards will run at this speed - LVDS and some of the lower voltage HSTL ones might. Furthermore, getting the clock to the OBUF is going to be complicated - you can't use a clock buffer, so it is unclear if you can use an OSERDES, which means routing the clock directly to the OBUF - this is highly discouraged. Assuming it works, the quality of the clock will be poor since it is running through general fabric routing.

But in any case, it still comes back to "what do you want to do with this". If you are trying to use the MMCM in the FPGA to generate a high speed clock for some external device, it is almost certain the clock you get will not be of sufficient quality - something that uses 933MHz clock will likely require a VERY clean clock - far cleaner than one coming from the FPGA's MMCM through an FPGA OBUF. Clocks like this should (must?) be generated by a dedicated clocking chip - something like the SI570 that is used on many of the Xilinx development boards for clock generation. In the KC705 (as an example) though, you cannot route this directly to a connector (it only goes to the SYSCLK pins of the FPGA).

Since you still haven't told us what this is for (other than "But for my application I need clock at least more than 900 MHz" which doesn't really tell us anything), we cannot help you any further.

Avrum

11 Replies
Teacher xilinxacct
Teacher
1,271 Views
Registered: ‎10-23-2018

Re: Getting Critical Warning “[Timing 38-282] The design failed to meet the timing requirements.”When tried to achieve output frequency of 930Mhz from clocking wizard IPcore using diff. input 200Mhz

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@mufasir_qureshi

I have not looked at your project file, but 714 'may' be approaching a reasonable limit for some designs and hardware.

One this you might try to squeeze out a few more cycles is turn on the -no_lc switch in the synthesis settings. That may use slightly higher LUT counts, but may result in a better routing.

If you find this helpful, please drop a KUDO and/or mark as 'solution accepted'

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Historian
Historian
1,256 Views
Registered: ‎01-23-2009

Re: Getting Critical Warning “[Timing 38-282] The design failed to meet the timing requirements.”When tried to achieve output frequency of 930Mhz from clocking wizard IPcore using diff. input 200Mhz

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While the MMCM can have a maximum frequency of 933MHz in your device, the BUFG (which is being driven by the MMCM) has a maximum frequency of 710MHz - see DS183, table 35 fMAX_BUFG.

In fact, no clock buffer can go at the full 933MHz (the fastest is the BUFIO at 800MHz, and that is only for high speed SERDES clocking). The 933MHz maximum for the MMCM is only useable by the memory interface generator (MIG) using "MEMORY" mode clocking of the ISERDES, which is not well documented since it is not supposed to be used directly by the user (only the MIG is supposed to use it).

And besides, what do you expect to be able to do at 933MHz? None of the fabric logic is rated to run at this speed - most of the fabric maxes out at around 550MHz or 600MHz in the faster speed grade (and getting things running at these speeds is VERY VERY challenging). Some I/O standards (particularly those used for DDR3/DDR4 memory interfaces) can run faster, but you must use serialization/deserialization with the OSERDES/ISERDES to get high speeds, and the highest speeds are only attainable through the MIG.

Avrum

1,214 Views
Registered: ‎12-30-2018

Re: Getting Critical Warning “[Timing 38-282] The design failed to meet the timing requirements.”When tried to achieve output frequency of 930Mhz from clocking wizard IPcore using diff. input 200Mhz

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Thanks for your response.

I have tried it but it makes not difference.

 Regards,

Mufasir Fida Qureshi

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1,213 Views
Registered: ‎12-30-2018

Re: Getting Critical Warning “[Timing 38-282] The design failed to meet the timing requirements.”When tried to achieve output frequency of 930Mhz from clocking wizard IPcore using diff. input 200Mhz

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Thanks for your kind and timely response. Your help is appreciated.

I have tried to interchange BUFG with BUFIO but clock wizard doesn’t have that option. Screen shot is attached. Please have a look. How can I change BUFFER within the Clocking wizard IPcore?????

Previously I already achieved 933 MHz as output clock at SMA connector (J33).Pic is attached.I am using VC707 kit.(You can confirm this using project file attached previously) But when I increase clock output more the 714 MHz it get little bit unstable with warning as mentioned earlier(thanks to you it is clear that it was because of buffer limitation).And it is appreciated. But for my application I need clock at least more than 900 MHz. How should I approach this issue????

 

Regards,

Mufasir Fida Qureshi

buff_info.png
results.jpg
buff_info.png
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Historian
Historian
1,161 Views
Registered: ‎01-23-2009

Re: Getting Critical Warning “[Timing 38-282] The design failed to meet the timing requirements.”When tried to achieve output frequency of 930Mhz from clocking wizard IPcore using diff. input 200Mhz

Jump to solution

First, in order to ensure that you are not using a BUFG, in the "Clocking Options" tab, you must deselect "Phase Alignment" - using "Phase Alignment" uses a BUFG between CLKFBOUT and CLKFBIN - turning it off uses the internal feedback path which doesn't limit the design to the frequency of the BUFG.

Then, once the clock is generated, it cannot use any clock buffer (since all the clock buffers have maximum frequencies less than 933). So, I repeat the question - what do you want to do with this? As I said, a clock of this speed is unusable inside the FPGA - none of the resources will run this fast. Are you simply trying to generate a clock going out of the FPGA at this speed? If so, it is unclear what you are going to get. Very few of the I/O standards will run at this speed - LVDS and some of the lower voltage HSTL ones might. Furthermore, getting the clock to the OBUF is going to be complicated - you can't use a clock buffer, so it is unclear if you can use an OSERDES, which means routing the clock directly to the OBUF - this is highly discouraged. Assuming it works, the quality of the clock will be poor since it is running through general fabric routing.

But in any case, it still comes back to "what do you want to do with this". If you are trying to use the MMCM in the FPGA to generate a high speed clock for some external device, it is almost certain the clock you get will not be of sufficient quality - something that uses 933MHz clock will likely require a VERY clean clock - far cleaner than one coming from the FPGA's MMCM through an FPGA OBUF. Clocks like this should (must?) be generated by a dedicated clocking chip - something like the SI570 that is used on many of the Xilinx development boards for clock generation. In the KC705 (as an example) though, you cannot route this directly to a connector (it only goes to the SYSCLK pins of the FPGA).

Since you still haven't told us what this is for (other than "But for my application I need clock at least more than 900 MHz" which doesn't really tell us anything), we cannot help you any further.

Avrum

1,104 Views
Registered: ‎12-30-2018

Re: Getting Critical Warning “[Timing 38-282] The design failed to meet the timing requirements.”When tried to achieve output frequency of 930Mhz from clocking wizard IPcore using diff. input 200Mhz

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Thanks for response.

After thoroughly going through the documents referred I got that I was approaching things wrongly. I may not require that much clock frequency but of course I need stable clock.

Your responses were very helpful for my understanding. Thanks again for that.

Regards,

Mufasir Fida Qureshi

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1,010 Views
Registered: ‎12-30-2018

Re: Getting Critical Warning “[Timing 38-282] The design failed to meet the timing requirements.”When tried to achieve output frequency of 930Mhz from clocking wizard IPcore using diff. input 200Mhz

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I am trying to use Analog to Digital converter (ADC12D1800) with Virtex-7 board .I have achieved 710Mhz stable frequency with VC707 but ADC12D1800 have output data rate of 1.8 GSPS (12-bits sample).

How should I approach this???Need to acquire maximum number of samples.

Problem statement: I want to use ADC with 1.8GSPS and doesn’t have much higher clock frequency of VC707 board. Please guide.

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Mentor hgleamon1
Mentor
1,000 Views
Registered: ‎11-14-2011

Re: Getting Critical Warning “[Timing 38-282] The design failed to meet the timing requirements.”When tried to achieve output frequency of 930Mhz from clocking wizard IPcore using diff. input 200Mhz

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Are you trying to generate the ADC sampling clock from the FPGA?

If so, are you sure that the FPGA can generate the necessary clean clock signal with reduced jitter, etc. for this application?

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"That which we must learn to do, we learn by doing." - Aristotle
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993 Views
Registered: ‎12-30-2018

Re: Getting Critical Warning “[Timing 38-282] The design failed to meet the timing requirements.”When tried to achieve output frequency of 930Mhz from clocking wizard IPcore using diff. input 200Mhz

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Yes. I want to generate sampling clock from FPGA.

I am sure that VC707 can generate clean clock up to 710MHz.

That’s the main point. I was able achieve 710MHz clean clock from VC 707 board and using this I can only acquire maximum 710 MSPS. But I want to achieve more data sample per second. How can I do that?

And how much maximum number of sample I can acquire from ADC12D1800 using VC 707 board???This is what I am trying to find out…..

Please guide.

Hopefully you are getting my point.  

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Mentor hgleamon1
Mentor
988 Views
Registered: ‎11-14-2011

Re: Getting Critical Warning “[Timing 38-282] The design failed to meet the timing requirements.”When tried to achieve output frequency of 930Mhz from clocking wizard IPcore using diff. input 200Mhz

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I see this thread is marked as solved but I have replied to your other thread.

----------
"That which we must learn to do, we learn by doing." - Aristotle
983 Views
Registered: ‎12-30-2018

Re: Getting Critical Warning “[Timing 38-282] The design failed to meet the timing requirements.”When tried to achieve output frequency of 930Mhz from clocking wizard IPcore using diff. input 200Mhz

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Ok.Thanks.

Regards,

Mufasir Fida Qureshi

 

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