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Contributor
Contributor
11,593 Views
Registered: ‎12-04-2014

Help : ISE output timing constraint

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Hi,

I'm designing an Spartan6 FPGA system. It receives oscillator CLK and generate internal clock CLK0 by DCM. The CLK0 drives data register D by rising edge , drives clock register C by falling edge. Add-on device receives clock C and data D by a register. For correctly transfer data, data D should be stable 1ns ahead of and after clock C rising.

The oscillator CLK and DCM CLK0 are both 100MHz, and output clock C are operating at 50MHz by dividing DCM clock CLK0.

How to constaint output pin C and D?

 

circuit_timing.jpg

I tried such a constraint as follow but add-on devices do not receive data corectly.

NET "D" OFFSET = IN 10 ns after "CLK" ;

NET "C" OFFSET = IN 11 ns after "CLK" ;

 

According to my understanding Such a constraint specifies maximum delay time(10 ns) from CLK rise to output pin D valid  and maximum delay time(11 ns) from CLK rise to output pin C.

But such a constraint do not specifies the minimun time from CLK rise to output pin D&C valid.

So such a constraint can not guarantee 1ns requirement in the figure.

 

How can I specifies the timing relationship between output D and C?

 

 

 

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Instructor
Instructor
20,934 Views
Registered: ‎08-14-2007

Re: Help : ISE output timing constraint

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There's one way to do what you want reliably, and that is to force the output flip-flops into the IOB.  In Verilog this would look like:

 

(* IOB = "FORCE" *) reg  D;

(* IOB = "FORCE" *) reg Q;

 

Then the output timing (clock to pad) is fixed and only depends on the clock phase feeding each of these flip-flops.  You could add an output constraint, but there's really nothing the tools can do to meet it if you don't design the output circuit correctly.

 

The constraints you have are for input signals (inputs to the FPGA) and don't do anything for output signals.  If you want to have a constraint so the timing report shows the clock to output delays, you should use OFFSET OUT AFTER constraints, which constrain the (maximum) time from clock arrival (CLK in your diagram) at the pin to output switching (D and C in your diagram) at the pins.  If you want more hints, search the forums for "source synchronous" to see other ways to implement what you want.

-- Gabor
6 Replies
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Instructor
Instructor
20,935 Views
Registered: ‎08-14-2007

Re: Help : ISE output timing constraint

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There's one way to do what you want reliably, and that is to force the output flip-flops into the IOB.  In Verilog this would look like:

 

(* IOB = "FORCE" *) reg  D;

(* IOB = "FORCE" *) reg Q;

 

Then the output timing (clock to pad) is fixed and only depends on the clock phase feeding each of these flip-flops.  You could add an output constraint, but there's really nothing the tools can do to meet it if you don't design the output circuit correctly.

 

The constraints you have are for input signals (inputs to the FPGA) and don't do anything for output signals.  If you want to have a constraint so the timing report shows the clock to output delays, you should use OFFSET OUT AFTER constraints, which constrain the (maximum) time from clock arrival (CLK in your diagram) at the pin to output switching (D and C in your diagram) at the pins.  If you want more hints, search the forums for "source synchronous" to see other ways to implement what you want.

-- Gabor
Xilinx Employee
Xilinx Employee
11,580 Views
Registered: ‎07-21-2014

Re: Help : ISE output timing constraint

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Hi,
As you are trying to constraint the output pins you need to use offset =out constraint.
please refer to following AR regarding this. this AR takes example with respect to ODDR but same can be applicable for registers.
http://www.xilinx.com/support/answers/34294.html

thanks,
Shreyas

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Instructor
Instructor
11,573 Views
Registered: ‎08-14-2007

Re: Help : ISE output timing constraint

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Just to clarify, the constraints in that answer record will check if your design meets the requirements for output D to output C skew.  It will not cause the outputs to meet the requirements if you don't design the outputs correctly.  In the schematic diagram you can see an ODDR used as an inverting clock output.  The standard register used as the data output should be forced into the IOB to match the timing delay of the ODDR (which can only be in an IOB).

-- Gabor
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Contributor
Contributor
11,551 Views
Registered: ‎12-04-2014

Re: Help : ISE output timing constraint

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Thank you very much.

I tried constrait in .ucf as follows

 

net "D" IOB = FORCE ;

net "C" IOB = FORCE ;

 

In pinout report, it shows neither of D and C is implemented as IO Register. So, I'm not confirmed if the constraint be implemented. Where can I confirm it?

The circuit does not work correctly.

 

 

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Contributor
Contributor
11,545 Views
Registered: ‎12-04-2014

Re: Help : ISE output timing constraint

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Thank you very much.

 

I tried constraint in .ucf as follows, r_D and r_C are internal register name:

 

NET "D" TNM = pad_group;

NET "C" TNM = pad_group;

INST "r_D" TNM = reg_group;

INST "r_C" TNM = reg_group;

 

TIMEGRP "pad_group" OFFSET = OUT 1 ns VALID 2 ns AFTER "clk" REFERENCE_PIN "C" TIMEGRP "reg_group";

 

is the constraint right according to my circuit? 

is the constaint specifys that minimum time from data D valid to rising of clock C as 1ns ?

is the constaint specifys that minimum time from rising of clock C to data D invalid as 2-1=1nS ?

 

 

The circuit work incorrectly when constaint as above.

 

 

 

 

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Contributor
Contributor
11,480 Views
Registered: ‎12-04-2014

Re: Help : ISE output timing constraint

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Thank you very much! It works !

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