03-01-2013 08:52 PM
I created a project with 64 instance of a custom core, the maximum frequency of the system is 460Mhz. However when I have 128 instance of a custom core, the maximum frequency is 100Mhz. For 8, 16 and 32 instance of this custom core is 480Mhz, 460Mhz and 450 Mhz respectively.
I looked at the system with 128 instances of the custom core with fpga_editor, and I noticed that logic is getting distributed extremely far away from each other.
My question is: Is there a constraints attribute that would allow the placer to do a better job (For example, RLOC_RANGE)?
Any tips, tricks or suggestions for this issue would be highly appreciated.
03-01-2013 10:35 PM
You can constraint each core by RLOC, that is, inside a core you can place the components of this core releatively. However some combinational things cannot be constrained such as and , or gates.
In addition to RLOC, you can try to constraint longest path delays in each core by grouping them.
03-02-2013 12:38 PM
Thank you for your reply. I played with the RLOC but I didn't get much progress, since I believe the issue is at the system level.
I was thinking if I can show the tools how a single instance of the pcore is placed and routed, I believe the tools would be able to use it as a template to place and route many instance of the pcore. Is this possible with the tools? If so how? Are there any tutorials/guidelines?
03-02-2013 11:34 PM
I did not it before however I think it is possible. Constraints can be embedded in VHDL code.If you embed it into VHDL code using RLOC & routing directives...., all of the in instances of core is mapped & routed in a such way you described.
Constraints Guide Page 18;
Implementation Constraints Implementation constraints are instructions given to the FPGA implementation tools to direct the mapping, placement, timing or other guidelines for the implementation tools to follow while processing an FPGA design. Implementation constraints are generally placed in the UCF file, but may exist in the HDL code, or in a synthesis constraints file.
03-05-2013 07:51 PM
So what I was thinking of is knwon as the "smartguide" techonology by Xilinx. Unfortunetely, it did not give the result I was expecting. I will try "RLOC" now.
03-08-2013 09:02 AM
Have you tried Pblocks to constraint the placement of those modules?
As a reference guide , I would suggest the "Floorplanning methodology" :
03-21-2013 10:14 PM
Thanks for the reply blasm. After some research I decided to use the AREA_GROUP contraint. I made my system with eight instances of an object par at 500 MHz, using an area dimension of 16 x 13 per object. I'm very pleased with this result. However, when I attempt to map a system with 16 instance of the same object, using the same dimensions I get the following error:
ERROR:Place:120 - There were not enough sites to place all selected components.
Some of these failures can be circumvented by using an alternate algorithm (though it may take longer run time). If
you would like to enable this algorithm please set the environment variable XIL_PAR_ENABLE_LEGALIZER to 1 and try
I incrementally increase the y dimension, but the error persists. I now get this error:
ERROR:MapHelpers:151 - Error while processing the area group range. Unable to
create a LOC object using the constraint SLICE_X64Y45:SLICE_X79Y89 attached
to area group router11. One or more ranges contain syntax error or illegal
site. Please modify the constraint.
There is no syntax error or invalid site. I'm using the ML605 board with the Virtex 6 LX240T chip, that has a slice grid layout of 162x240. I attached the latest ucf file for my system with 16 instance of the object.
Any suggestions, guidance or help would be appreciated. Thanks!