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Contributor
Contributor
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Registered: ‎03-06-2009

Hold Violation

All,

 

I am having a trouble correcting a hold violation during synthesis in an EDK 10.1 project.  Am I correct in that a hold violation represents a data path reaching a point in logic well before the clock signal reaches the same point in the logic path?  I am also including a snippet of the Trace report.  My custom peripheral uses an A/D clock @ 18.66667 MHz to drive a DCM which must produce a 56 MHz clock to drive a digital drop receiver.  Any thoughts on what I could do?

 


================================================================================ Timing constraint: TS_digital_drop_receiver_0_digital_drop_receiver_0_USER_LOGIC_I_ADC_Clkt = PERIOD TIMEGRP "digital_drop_receiver_0_digital_drop_receiver_0_USER_LOGIC_I_ADC_Clkt" 18 ns HIGH 50%; 251230 paths analyzed, 9883 endpoints analyzed, 860 failing endpoints 860 timing errors detected. (0 setup errors, 860 hold errors) Minimum period is 11.072ns. -------------------------------------------------------------------------------- Hold Violations: TS_digital_drop_receiver_0_digital_drop_receiver_0_USER_LOGIC_I_ADC_Clkt = PERIOD TIMEGRP "digital_drop_receiver_0_digital_drop_receiver_0_USER_LOGIC_I_ADC_Clkt" 18 ns HIGH 50%; -------------------------------------------------------------------------------- Hold Violation: -2.702ns (requirement - (clock path skew + uncertainty - data path)) Source: digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/adc_cnts_1 (FF) Destination: digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/Inst_DDC_9479/CIC_Mod_I/i1_81 (FF) Requirement: 0.000ns Data Path Delay: 1.539ns (Levels of Logic = 1) Positive Clock Path Skew: 4.096ns (5.456 - 1.360) Source Clock: digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/ADC_Clkt rising at 0.000ns Destination Clock: digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/DDC_Clk_A rising at 18.000ns Clock Uncertainty: 0.145ns Clock Uncertainty: 0.145ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.000ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.289ns Phase Error (PE): 0.000ns Minimum Data Path: digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/adc_cnts_1 to digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/Inst_DDC_9479/CIC_Mod_I/i1_81 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X60Y40.YQ Tcko 0.331 digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/adc_cnts<0> digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/adc_cnts_1 SLICE_X60Y40.F1 net (fanout=7) 0.546 digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/adc_cnts<1> SLICE_X60Y40.X Tilo 0.179 digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/adc_cnts<0> digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/Inst_DDC_9479/ADC_D_12_and000011_1 SLICE_X56Y40.CE net (fanout=190) 0.504 digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/Inst_DDC_9479/ADC_D_12_and000011 SLICE_X56Y40.CLK Tckce (-Th) 0.021 digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/Inst_DDC_9479/CIC_Mod_I/i1<80> digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/Inst_DDC_9479/CIC_Mod_I/i1_81 ------------------------------------------------- --------------------------- Total 1.539ns (0.489ns logic, 1.050ns route) (31.8% logic, 68.2% route)

 

Thanks,

David

 

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Advisor
Advisor
7,345 Views
Registered: ‎12-03-2007

It might be that the clock domain crossing is not constrained:

 

Source Clock: digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/ADC_Clkt rising at 0.000ns

Destination Clock: digital_drop_receiver_0/digital_drop_receiver_0/USER_LOGIC_I/DDC_Clk_A rising at 18.000ns

 

 

OutputLogic 

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Contributor
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So the relationship between these two clocks if through a BUFGMUX, likeso:

 

  ddc_clk_mux1: BUFGMUX
  port map (
        I0     => '0',                  
        I1     => ADC_Clkt,           
        S      => Power_On_A, 
        O      => DDC_Clk_A);

 

Essentially when Power_On_A is '1', the clocks are the exact same clock.  Does the lack of constraint arise in the case when Power_On_A is '0'?

 

Thanks,

David 

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Advisor
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Registered: ‎12-03-2007

It might. 

You can check if that path is in the "Unconstrained Paths" section of the timing report.

 

 

 OutputLogic

 

 

 

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