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Participant saurabhsk
Participant
7,508 Views
Registered: ‎02-17-2009

How UCF should be write if design is having DCM.

Hi,

 

  I am facing a problem in understanding the UCF.

 

I am explaining the design requirement in brief:

 

 I am having a 10ns input clock and that is going to an DCM . This DCM generates 2 clock CLK0 with 10ns and CLKFX with 5ns period. Both the clocks are in same phase to input clock. Now my one output "data_err" is getting derived on CLFFX - 5ns period.

 

As a constraints i define input clock as 10 ns and IO delays as 1 ns. In synthesis ,timing calculation calculation for data_err port will be like that this should meet the timing in 4ns, because it is getting derived from CLKFX (5ns - 1ns = 4ns requirement). As in UCF , i can only specify IO offset with respect to system input clock of 10 ns . SO i am seeing valur offset is 9ns . That's why PnR is trying to meet data_err in 9 ns . In other words PnR is trying to meet this path in 9ns which should be 4 ns conceptually.

 

So, my doubt is that what should be the expected behavior . I mean is there any chance that we will break any scenario on board due to this.

And if my observation is right then how can we pass this information through UCF to PnR tool.

 

Thanks in advance.

 

-Saurabh

 

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3 Replies
Xilinx Employee
Xilinx Employee
7,463 Views
Registered: ‎08-10-2008

Re: How UCF should be write if design is having DCM.

Can you show how you define the IO delay as 1 ns?

 

Since your driver clock is 5ns, you can specify the OFFSET OUT constraint as 4 ns or less.

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Participant saurabhsk
Participant
7,454 Views
Registered: ‎02-17-2009

Re: How UCF should be write if design is having DCM.

Thanks for the reply.

 

 To my synthesis tool , i gave global constraint:

 

  setup_deign -frequency 100 -input_delay 1ns -output_delay 1ns

 

As sys_clk(10ns)  is my input clock and DCM generated clocks are CLK0(10ns)  and CLKFX(5ns) . "data_err" is the output which has been getting derived by some flops whose clock is CLKFX(5ns) .Flops are ==> err_reg1 and err_reg2

 

 SO after synthesis my tool is generating UCF for PnR , then what is the expected UCF for data_err output port.

 

1.

 

NET "sys_clk" TNM_NET = "xmplr_sys_clk";
TIMESPEC "TS_clk_ClockDomain0" = PERIOD "xmplr_sys_clk" 10.000000 ns HIGH 50.000000 % ;

 

NET data_err TNM=TNMGRP0;
TIMEGRP ARVG0 =  TNMGRP0 ;
TIMEGRP ARVG0 OFFSET = OUT 9.000000 ns BEFORE "sys_clk";

 

 

2. 

 

NET "sys_clk" TNM_NET = "xmplr_sys_clk";
TIMESPEC "TS_clk_ClockDomain0" = PERIOD "xmplr_sys_clk" 10.000000 ns HIGH 50.000000 % ;

NET data_err TNM=TNMGRP0;
TIMEGRP ARVG0 =  TNMGRP0 ;
TIMEGRP ARVG0 OFFSET = OUT 4.000000 ns BEFORE "sys_clk";

 

3. 

 

NET "sys_clk" TNM_NET = "xmplr_sys_clk";
TIMESPEC "TS_clk_ClockDomain0" = PERIOD "xmplr_sys_clk" 10.000000 ns HIGH 50.000000 % ;

 

NET data_err TNM=TNMGRP1;

 

NET inst1/err_reg1 TMN= TNMGRP2;

NET inst1/err_reg2 TMN= TNMGRP2;

 

TIMESPEC TS_0 = FROM TNMGRP2 TO TNMGRP1 4.0 ns;

 

 

 

Which one is the correct UCF output for PnR ??

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Xilinx Employee
Xilinx Employee
7,448 Views
Registered: ‎08-10-2008

Re: How UCF should be write if design is having DCM.

I'd prefer option 3, but make some changes for the TNMGRP1.

 

3. 

 

NET "sys_clk" TNM_NET = "xmplr_sys_clk";
TIMESPEC "TS_clk_ClockDomain0" = PERIOD "xmplr_sys_clk" 10.000000 ns HIGH 50.000000 % ;

 

NET data_err TNM=PADS TNMGRP1;

 

NET inst1/err_reg1 TMN= TNMGRP2;

NET inst1/err_reg2 TMN= TNMGRP2;

 

TIMESPEC TS_0 = FROM TNMGRP2 TO TNMGRP1 4.0 ns; 

 

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