06-18-2009 06:28 AM
I want to implement a DDR2 controller using Virtex-5 FPGA . When I do length matching, how can I count in the signal delay caused by FPGA's package.
Or how can I get the clk to pad delay for each I/O signals?
06-18-2009 04:40 PM - edited 06-19-2009 05:04 AM
Other options include partgen, ADEPT, and PlanAhead:
http://www.xilinx.com/support/answers/22814.htm (8.1 Timing Virtex-II Pro/Virtex-4 - How do I calculate the flight time for my device?)
Fixed ADEPT link to its new location