08-06-2019 03:01 AM
I am working with virtex-6 FPGA. I have data signal that is coming from ADC and a clock signal from MMCM which I want to align. I wanted to use the constraint 'OFFSET' to achieve the same. However I saw the following paragraph in UG625(Xilinx Constraints Guide) and kind of got confused.
"Because the constraint specifies
the clock and data relationship at the external pads of the FPGA, the Offset In constraint
cannot be specified using an internal clock net. However, the Offset In constraint
automatically accounts for any phase or delay adjustments on the clock path due to
components such as the DCM, PLL, MMCM, or IDELAY when analyzing the setup
and hold timing requirements at the capturing synchronous element. In addition, the
constraint propagates through the clock network and automatically applies to all clocks
derived from the original external clock."
Can someone tell me if the constraint can be used, cannot be used or does the alignment automatically?
Thanks in advance
08-06-2019 08:19 PM
You need to use the external input clock on the FPGA input pad in the OFFSET constraint. The tool will count the delay from the input pad to the MMCM output into the calculation of the timing path analysis.
The time value in the OFFSET IN constraint is the time difference between the external clock and the input data when they arrive at the FPGA pads.
08-06-2019 09:49 PM - edited 08-06-2019 09:57 PM
Hello @viviany ,
I am also trying to apply a phase shift to MMCM clock output w.r.t the input clock of MMCM. From what you said, I infer the following, please correct me if I am wrong.
->'The time value in the OFFSET IN constraint is the time difference between the external clock and the input data when they arrive at the FPGA pads.' : From this, if o/p of MMCM were to have a phase lead of some value w.r.t i/p of MMCM, I will have to subtract this lead value and write the OFFSET IN constraint so that I will get the required data delay w.r.t o/p clk of MMCM
Eg. If the o/p clk of MMCM has a lead of 5 ns w.r.t its input clock(which is the external clock at the input pad of Virtex-6 board) and I want the data to appear at a flip-flop, 7 ns before the positive edge of o/p clk of MMCM, I will have to write
OFFSET =IN 2 ns BEFORE mmcm_clk_i/p which is equivalent to saying
OFFSET=IN 7 ns BEFORE mmcm_clk_o/p (This is what I want)
Please tell me if this is possible..
Thanks in advance
08-06-2019 11:25 PM