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Visitor
318 Views
Registered: ‎01-22-2019

## How long does it take to complete a process in VHDL, using Vivado

I have a lot of processes on my VHDL project some may have a few lines of code, however there are few with a lot of lines. So my question is, How long does a process take to complete the secuential order from my first instruction to the last one? I would like to know if there is a method in wich I can calculate it or simulate it. thanks

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Scholar
277 Views
Registered: ‎06-21-2017

## Re: How long does it take to complete a process in VHDL, using Vivado

Are these registered processes, that is are they running on a clock edge?  If so, the process runs on every clock.  Remember, this is hardware not a sequential instruction computer.  Every line can be executed in parallel. For instance

```example1: process(clk)
begin;
if rising_edge(clk) then
Mia_1 <= Mia_in;
Mia_2 <= Mia_1;
Mia_out <= Mia_2;
end if;
end process;```

The process accepts a new input on every clock and produces an output on every clock.  The throughput of the process is one bit per clock.  It requires three clock cycles for the value of  the signal Mia_in to be shifted to the signal Mia_out.  The latency of this process is three clocks.  It isn't clear from your question if you are asking about latency or throughput.  Both are code dependent but the process runs on every clock.

You can use a clock enable to control your process.

```example2: process(clk);
begin;
if rising_edge(clk) then
if (clk_en = '1') then
Mia_out <= Mia_in;
end if;
end if;
end process;```

The register that this process instantiates is still clocked on every clock edge, but Mia_out only changes if clk_en is a '1'.  The latency of this process is one clock, but the throughput is dependent on how often clk_en is high.

For long, comples processes, the best way to determine latency is probably to simulate your circuit.

3 Replies
Highlighted
Scholar
278 Views
Registered: ‎06-21-2017

## Re: How long does it take to complete a process in VHDL, using Vivado

Are these registered processes, that is are they running on a clock edge?  If so, the process runs on every clock.  Remember, this is hardware not a sequential instruction computer.  Every line can be executed in parallel. For instance

```example1: process(clk)
begin;
if rising_edge(clk) then
Mia_1 <= Mia_in;
Mia_2 <= Mia_1;
Mia_out <= Mia_2;
end if;
end process;```

The process accepts a new input on every clock and produces an output on every clock.  The throughput of the process is one bit per clock.  It requires three clock cycles for the value of  the signal Mia_in to be shifted to the signal Mia_out.  The latency of this process is three clocks.  It isn't clear from your question if you are asking about latency or throughput.  Both are code dependent but the process runs on every clock.

You can use a clock enable to control your process.

```example2: process(clk);
begin;
if rising_edge(clk) then
if (clk_en = '1') then
Mia_out <= Mia_in;
end if;
end if;
end process;```

The register that this process instantiates is still clocked on every clock edge, but Mia_out only changes if clk_en is a '1'.  The latency of this process is one clock, but the throughput is dependent on how often clk_en is high.

For long, comples processes, the best way to determine latency is probably to simulate your circuit.

Explorer
219 Views
Registered: ‎07-18-2018

## Re: How long does it take to complete a process in VHDL, using Vivado

bruce gave a good explination, but a few other things to mention.

If you don't understnad what is happening in a process, you can write a test bench and simulate it using the vivaod simulator. If will step through your logic, and let you know at each clock what the expected values will be. So you can confirm what you expect is being cacualted, and how many clock cycles it takes based on your HW description.

The next is that if you provide a clock constraint, and implement, if will let you know if all the steps per clock in your process can be completed. You can see the total time of the combinational elements that are computed for the process.

So if you need to do a lot of things that have sequential dependency of the operations in a process, if it won't work at a given speed, the tools will let you know. Which is usually a good indication to break it up into multiple steps by inserting pipeline registers, or trying to solve the problem with a state machine.

Scholar
212 Views
Registered: ‎07-09-2009

## Re: How long does it take to complete a process in VHDL, using Vivado

Your comming at this from a processor background.

It does not apply in HDL's ,

Your writting code that generates hard ware,