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ronnu
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Registered: ‎10-14-2017

How "much" logic can I "fit" in one clock cycle?

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Hi,

I'm currently working on design where I need to do a fair bit of calculations with unsigned numbers (addition, subraction, comparisement etc.). I developed an algorithm and implemented it in VHDL. In my first approach I wrote a single process which did multiple sequential calculations on a single clock edge. Then I started wondering if this might induce some timing errors as all those calculations take some amount of time.

I'm sure Vivado synthesisis and simulation tools are intelligent enough to check and report if any timing violations are present. Also, I understand that this all depends on the specific clock rate, slew rate etc. However, what I would like to know if there is maybe any rough estimation on how "much" logic can we "fit" into once clock cycle (sorry, I do not know how to describe this better) and what is the best practice. What I mean is, if my logic has to, for example, perform ten sequential additions with say 14bit unsigned numbers, then would there be a problem with timing if my clock rate is 25MHz? What if my clock rate is 300MHz? Or is it maybe that in practice I would not have to worry about this kind of thing because reaching a limit this way is unrealistic? 

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dgisselq
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Registered: ‎05-21-2015

@ronnu,

@tedboothreally has the "right" answer to this question.  I wrote about it some time ago, trying to capture all of the parts and pieces to the question.

Since that time, some one suggested the following path.  (Should sound very much like @tedbooth 's answer)

  1. Pick the clock frequency you are interested in
  2. Start building your logic
  3. If it doesn't fit at the clock frequency you are interested in, adjust (add more pipeline stages, simplify logic, removing cascaded multiplexers, etc.)

When you are done with this, you should have a good feel for what will and will not fit.

For me, I like to use the rule of thumb that a 32-bit adder plus a multiplexer selecting among multiple adder (or comparator) outputs will fit in one clock period.  This also fixes my clock period at about 100MHz for my Arty board.  This same rule of thumb translates to close to 160MHz on a Virtex-7 board, about 80MHz on a Spartan 6 board, about 50MHz on an iCE40 HX board, 60MHz on an ECP5, etc.

Dan

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tedbooth
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Registered: ‎03-28-2016

To my knowledge, there is no rule of thumb that can be followed for how much logic can fit in one clock cycle.  There are just so many variables to that problem.  Obviously, the faster the clock the less logic that can be fit while the slower the clock the more logic that can be fit. 

Sometimes the best thing to do is to write your code with a moderate amount of pipelining.  Add your timing constraints and run synthesis on your code.  Check the timing reports after synthesis.  If you meet timing, your good to go.  If your don't, then go back to your code and add additional pipelining.  Use the failing paths in the post-synthesis timing reports to guide your as to where best add the additonal pipelining.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
xilinxacct
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Registered: ‎10-23-2018

@ronnu 

If I interpret your question correctly... For the first half of your question, you can theoretically fit as much logic in a single clock cycle that can be handled using purely combinational logic, and no internal data dependancies. (e.g. once the clock has triggered the logic, it will flow to completion). As such, if you can also do some of the in parallel, all the better... The second part is the clock speed... That will be limited by what the propogation time is.

Hope that Helps

If so, Please mark as solution accepted. Kudos also welcomed. :-)

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dgisselq
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Scholar
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Registered: ‎05-21-2015

@ronnu,

@tedboothreally has the "right" answer to this question.  I wrote about it some time ago, trying to capture all of the parts and pieces to the question.

Since that time, some one suggested the following path.  (Should sound very much like @tedbooth 's answer)

  1. Pick the clock frequency you are interested in
  2. Start building your logic
  3. If it doesn't fit at the clock frequency you are interested in, adjust (add more pipeline stages, simplify logic, removing cascaded multiplexers, etc.)

When you are done with this, you should have a good feel for what will and will not fit.

For me, I like to use the rule of thumb that a 32-bit adder plus a multiplexer selecting among multiple adder (or comparator) outputs will fit in one clock period.  This also fixes my clock period at about 100MHz for my Arty board.  This same rule of thumb translates to close to 160MHz on a Virtex-7 board, about 80MHz on a Spartan 6 board, about 50MHz on an iCE40 HX board, 60MHz on an ECP5, etc.

Dan

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ronnu
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Explorer
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Registered: ‎10-14-2017

Thank you for the replies.

dgisselq, I read your article and I think that more-or-less answered my questions. I'm still a beginner at FPGA design and although I've done some simple designs on hardware I have not used any timing constraints so far. But now that I've started pondering around with Zynq-7000 and have a bigger design at hand I guess it's time to start learning about timing constraints.

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