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Contributor
Contributor
6,966 Views
Registered: ‎06-22-2009

How to constrain a bus?

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Hi!

 

I'm not very experienced in constraining and i've a problem with a design and i think adding some constrains will solve it.

 

In my design is a broad (ca 1024bit) data bus system running through several serial processing stages:

 

===BUS[1023 downto 0]====> STAGE 1 =======> STAGE 2 =====>...

 

Every stage is build of several parallel processing blocks with an input and output width of 128bit. I'm instancing the stages and distributing the bus parallel to the stages and after the stage I collect all the outputs again to another broad bus systemconnected to the next stage.

 

Now my problem: After running through several stages, the bus isn't synchronous anymore. bit 0 to 511 is in sync and bit 512 to 1023 is shifted by 4 clocks. How can I tell the synthesizer to treat the bus as a parallel and syncronous system???

 

thank you,

Jonas

 

 

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Voyager
Voyager
8,071 Views
Registered: ‎08-30-2007

You mention you run the bus though "several serial processing stages".

 

a) I assume the processing stages have pipeline registers in them?

b) Are the stages identical, or do they have different levels of pipelining?

 

If they are pipelined, the only legitimate reason for the 2 halves of the bus to be

out of sync is if they have different pipelling depths.  You'll need to adjust the

logic to have identical pipeline depths so the data lines up.

 

If the logic is combinatorial, you may have some serious timing problems if you

have 4 clock cycle difference between the bus timing.

 

John Providenza

 

 

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Advisor
Advisor
6,952 Views
Registered: ‎12-03-2007

It sounds like all you need to do is to add 4 register stages to bits [0:511] of your bus to synchronize with bits [512:1023].

 

 OutputLogic

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Contributor
Contributor
6,937 Views
Registered: ‎06-22-2009

thank you for your reply !

 

your solution sounds ok but i'm wondering if there isn't a way to tell the synthesizer to automaticaly do inserting registers to keep the bus in sync. because simulating my design is very time-consuming...

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Voyager
Voyager
8,072 Views
Registered: ‎08-30-2007

You mention you run the bus though "several serial processing stages".

 

a) I assume the processing stages have pipeline registers in them?

b) Are the stages identical, or do they have different levels of pipelining?

 

If they are pipelined, the only legitimate reason for the 2 halves of the bus to be

out of sync is if they have different pipelling depths.  You'll need to adjust the

logic to have identical pipeline depths so the data lines up.

 

If the logic is combinatorial, you may have some serious timing problems if you

have 4 clock cycle difference between the bus timing.

 

John Providenza

 

 

View solution in original post

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Contributor
Contributor
6,905 Views
Registered: ‎06-22-2009

Hi !

 

You're right, it was a issue of different-length pipelining...

 

Thank you for your support!

Jonas

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