UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
4,311 Views
Registered: ‎03-13-2014

How to constrain an input strap?

Jump to solution

Hi,

 

I am new to Vivado and have a problem constraining inputs, the design is in Verilog and targets a Zynq. I have what I call straps, input pins that are either pulled high or low with a resistor. So they don't change and are 'fixed' the moment the logic is configured. However that creates lots of warnings about timing.

 

On a related theme, how should an input be constrained if it is aync and goes to a synchroniser flip/flop.

 

Thanks

0 Kudos
1 Solution

Accepted Solutions
Scholar pedro_uno
Scholar
7,629 Views
Registered: ‎02-12-2013

Re: How to constrain an input strap?

Jump to solution

Vivado adopted the SDC style of timing constraints.  In the absence of an overriding constraint SDC assumes that I/O pins will need to meet the same period constraint that is assigned to the clock running the flip-flop.  Often it is impossible for an I/O pin to meet that constraint.  For example a 200MHz clock frequency would require less than 5ns clock-to-out timing.

 

I like to use the "set_max_delay" command in my .xdc files to set reasonable timing requirements on the types of "strapped" and asynchronous i/o you describe.  You can set the constraint to say 20ns which will cause the timing reports to be quiet on those pins.

 

Good luck.

----------------------------------------
DSP in hardware and software
-----------------------------------------
0 Kudos
5 Replies
Scholar pedro_uno
Scholar
7,630 Views
Registered: ‎02-12-2013

Re: How to constrain an input strap?

Jump to solution

Vivado adopted the SDC style of timing constraints.  In the absence of an overriding constraint SDC assumes that I/O pins will need to meet the same period constraint that is assigned to the clock running the flip-flop.  Often it is impossible for an I/O pin to meet that constraint.  For example a 200MHz clock frequency would require less than 5ns clock-to-out timing.

 

I like to use the "set_max_delay" command in my .xdc files to set reasonable timing requirements on the types of "strapped" and asynchronous i/o you describe.  You can set the constraint to say 20ns which will cause the timing reports to be quiet on those pins.

 

Good luck.

----------------------------------------
DSP in hardware and software
-----------------------------------------
0 Kudos
Historian
Historian
4,286 Views
Registered: ‎01-23-2009

Re: How to constrain an input strap?

Jump to solution

In the absence of an overriding constraint SDC assumes that I/O pins will need to meet the same period constraint that is assigned to the clock running the flip-flop. 

 

This isn't technically true.

 

Static timing analysis in Vivado is always path based - it looks at a path that starts at a clocked startpoint, ends at a clocked endpoint and comprises the nets and combinatorial cells between them. The requirement on the path is determined by the relationship between the clock at the startpoint and endpoint. This is true regardless of whether the path is purely internal to the FPGA or is partly inside and partly outside the FPGA.

 

In the case of any input, the path starts outside the FPGA. As a result, the tool cannot (yet) know either the clock that clocks the startpoint, nor the delay through "components" on the path from the startpoint to the port (i.e. the portion of the path outside the FPGA). This is the role of the set_input_delay command - you tell the tool what clock clocks the startpoint and the delay from the startpoint clock to the FPGA port.

 

So, without a set_input_delay, the "stuff" inside the FPGA between the package pin (the port) and the capture flop are not constrained - I won't call it a path, since it doesn't become a path until the set_input_delay is executed on the port. As a result, it cannot fail timing. Even if it were a path, it would be a classic false path since it can't make a transition.

 

In your case, you could probably leave it this way. The input pin is static, hence it makes no transitions, hence there is no "timing" to worry about. However, Vivado checks for inputs with no set_input_delay as part of the check_timing command (that is run by default in project mode). It will flag this input with a warning.

 

If you want to remove the warning from check_timing, then put a set_input_delay on the port. You can literally use any clock that exists and specify any delay that you want. Now this is a path, and check_timing will be happy. But, as I said above, it is a false path and should be declared as such with

 

set_false_path -from [get_ports <port_name>]

 

This will disable the timing checks on the port, which is appropriate if it really is a strap. And if it is a strap, you don't even need a synchronizer on it - if it can't make a transition, then timing is not an issue. That being said, I would probably put a 2 stage synchronizer on it anyway, since I am philosophically opposed to using an asynchronous input in a system, and the two FF synchronizer is really cheap...

 

Avrum

Instructor
Instructor
4,283 Views
Registered: ‎08-14-2007

Re: How to constrain an input strap?

Jump to solution

"On a related theme, how should an input be constrained if it is aync and goes to a synchroniser flip/flop."

 

As Avrum said, there are a number of ways to constrain the timing, if you want to get rid of warnings.  In any case, the "synchronizer flip/flop" should have the ASYNC_REG property set like:

 

(* ASYNC_REG = "TRUE" *) reg sync_flop;

 

where sync_flop is the input register.

-- Gabor
0 Kudos
Explorer
Explorer
4,252 Views
Registered: ‎03-13-2014

Re: How to constrain an input strap?

Jump to solution

Thanks to everyone who replied. 

 

First off Pedro, the set_max_delay helps and seems to be a quick and easy way of removing the timing errors. Because of the 'failed' timing the run time for the route phase was getting extreme. I have taken that advice and trying to remove the errors today.

 

Avrum, that seems to be the correct way to do it with timing to maybe a virtual clock then declare the path as false. I will try that if the other way has problems

 

Gabor, thanks for the advice I already use the ASYNC_REG directive but that does not help with failed paths.

 

Thanks again

 

Dave

 

 

0 Kudos
Adventurer
Adventurer
1,244 Views
Registered: ‎06-22-2018

Re: How to constrain an input strap?

Jump to solution

I encountered the same problem. In my case, it's a ADC's 'OTR' (Out of Range) output pin, which is async to the ADC's sampling clock. 

 

You suggested 'set_false_path -from [get_ports <port_name>]'. Will 'set_disable_timing [get_ports <>] do the same thing? Which one is better?

 

Thanks.

0 Kudos